Intel 8XC196K Series User Manual page 15

CONTENTS
Figure
9-1 DPRAM vs Slave-Port Solution ....................................................................................9-2
9-2 Slave Port Block Diagram.............................................................................................9-3
9-3 Master/Slave Hardware Connections ...........................................................................9-7
9-4 Standard Slave Mode Timings (Demultiplexed Bus) ..................................................9-10
9-5 Standard or Shared Memory Mode Timings (Multiplexed Bus)..................................9-13
9-6 Slave Port Control (SLP_CON) Register....................................................................9-15
9-7 Slave Port Status (SLP_STAT) Register ....................................................................9-17
10-1 EPA Block Diagram ....................................................................................................10-2
10-2 EPA Timer/Counters ..................................................................................................10-6
10-3 Quadrature Mode Interface ........................................................................................10-8
10-4 Quadrature Mode Timing and Count ..........................................................................10-9
10-5 A Single EPA Capture/Compare Channel ................................................................10-10
10-6 EPA Simplified Input-Capture Structure ...................................................................10-11
10-7 Valid EPA Input Events ............................................................................................10-12
10-8 Timer 1 Control (T1CONTROL) Register .................................................................10-18
10-9 Timer 2 Control (T2CONTROL) Register .................................................................10-19
EPA Control (EPA x _CON) Registers .......................................................................10-21
10-10
10-11 EPA Compare Control (COMP x _CON) Registers....................................................10-25
10-12 EPA Interrupt Mask (EPA_MASK) Register .............................................................10-27
10-13 EPA Interrupt Mask 1 (EPA_MASK1) Register ........................................................10-27
10-14 EPA Interrupt Pending (EPA_PEND) Register.........................................................10-28
10-15 EPA Interrupt Pending 1 (EPA_PEND1) Registers ..................................................10-29
10-16 EPA Interrupt Priority Vector Register (EPAIPV)......................................................10-30
11-1 A/D Converter Block Diagram ....................................................................................11-1
11-2 A/D Test (AD_TEST) Register....................................................................................11-5
11-3 A/D Result (AD_RESULT) Register — Write Format .................................................11-6
11-4 A/D Time (AD_TIME) Register ...................................................................................11-7
11-5 A/D Command (AD_COMMAND) Register ................................................................11-8
11-6 A/D Result (AD_RESULT) Register — Read Format...............................................11-10
11-7 Idealized A/D Sampling Circuitry ..............................................................................11-11
11-8 Suggested A/D Input Circuit .....................................................................................11-13
11-9 Ideal A/D Conversion Characteristic.........................................................................11-16
11-10 Actual and Ideal A/D Conversion Characteristics.....................................................11-17
11-11 Terminal-based A/D Conversion Characteristic .......................................................11-19
12-1 A System Using CAN Controllers ...............................................................................12-1
12-2 CAN Controller Block Diagram ...................................................................................12-2
12-3 CAN Message Frames ...............................................................................................12-7
12-4 A Bit Time as Specified by the CAN Protocol...........................................................12-10
12-5 A Bit Time as Implemented in the CAN Controller ...................................................12-11
12-6 CAN Control (CAN_CON) Register ..........................................................................12-13
12-7 CAN Bit Timing 0 (CAN_BTIME0) Register..............................................................12-15
12-8 CAN Bit Timing 1 (CAN_BTIME1) Register..............................................................12-16
12-9 CAN Standard Global Mask (CAN_SGMSK) Register .............................................12-18
12-10 CAN Extended Global Mask (CAN_EGMSK) Register ............................................12-19
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FIGURES
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