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Mnemonic
ANDB
LOGICAL AND BYTES. ANDs the two source
(3 operands)
byte operands and stores the result into the
destination operand. The result has ones in
only the bit positions in which both operands
had a "1" and zeros in all other bit positions.
←
(DEST)
Z
BMOV
BLOCK MOVE. Moves a block of word data
from one location in memory to another. The
source and destination addresses are
calculated using the indirect with autoin-
crement addressing mode. A long register
(PTRS) addresses the source and destination
pointers, which are stored in adjacent word
registers. The source pointer (SRCPTR) is
the low word and the destination pointer
(DSTPTR) is the high word of PTRS. A word
register (CNTREG) specifies the number of
transfers. The blocks of data can be located
anywhere in register RAM, but should not
overlap.
←
COUNT
LOOP: SRCPTR
←
DSTPTR
(DSTPTR)
←
(PTRS)
(PTRS + 2)
←
COUNT
if COUNT
go to LOOP
Z
—
Table A-6. Instruction Set (Continued)
Operation
(SRC1) AND (SRC2)
PSW Flag Settings
N
C
V
VT
0
0
—
(CNTREG)
←
(PTRS)
(PTRS + 2)
←
(SRCPTR)
SRCPTR + 2
←
DSTPTR + 2
COUNT – 1
≠
0 then
PSW Flag Settings
N
C
V
VT
—
—
—
—
INSTRUCTION SET REFERENCE
Instruction Format
DEST, SRC1, SRC2
ANDB
Dbreg, Sbreg, baop
(010100aa) (baop) (Sbreg) (Dbreg)
ST
—
PTRS, CNTREG
BMOV
lreg, wreg
(11000001) (wreg) (lreg)
NOTE: The
mented during this instruction.
However, CNTREG is not decre-
mented. Therefore, it is easy to
unintentionally
uninterruptible operation with the
BMOV
BMOVI instruction for an interrupt-
ible operation.
ST
—
pointers
are
autoincre-
create
a
long,
instruction.
Use
the
A-9
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