Intel 8XC196K Series User Manual page 510

Name Type
AD15:0 I/O
ADV# O
AINC# I
ALE O
ANGND GND
† This signal is not implemented on the 8XC196J x or 87C196CA (see "Design Considerations for
8XC196JQ, JR, JT, and JV Devices" on page 2-14 or "Design Considerations for 87C196CA Devices" on
page 2-13).
†† This signal is not implemented on the 8XC196J x (see "Design Considerations for 8XC196JQ, JR, JT, and
JV Devices" on page 2-14).
Table B-6. Signal Descriptions (Continued)
Address/Data Lines
These pins provide a multiplexed address and data bus. During the address
phase of the bus cycle, address bits 0–15 are presented on the bus and can be
latched using ALE or ADV#. During the data phase, 8- or 16-bit data is trans-
ferred.
AD7:0 are multiplexed with SLP7:0
multiplexed with P4.7:0 and PBUS.15:8.
Address Valid
This active-low output signal is asserted only during external memory
accesses. ADV# indicates that valid address information is available on the
system address/data bus. The signal remains low while a valid bus cycle is in
progress and is returned high as soon as the bus cycle completes.
An external latch can use this signal to demultiplex the address from the
address/data bus. A decoder can also use this signal to generate chip selects
for external memory.
On the 8XC196K x , ADV# is multiplexed with P5.0, SLPALE, and ALE.
On the 8XC196J x and 87C196CA, ADV# is multiplexed with P5.0 and ALE.
Auto Increment
During slave programming, this active-low input enables the auto-increment
feature. (Auto increment allows reading or writing of sequential OTPROM
locations, without requiring address transactions across the PBUS for each
read or write.) AINC# is sampled after each location is programmed or dumped.
If AINC# is asserted, the address is incremented and the next data word is
programmed or dumped.
On the 8XC196K x , AINC# is multiplexed with P2.4 and INTOUT#.
On the 8XC196J x and 87C196CA, AINC# is multiplexed with P2.4.
Address Latch Enable
This active-high output signal is asserted only during external memory cycles.
ALE signals the start of an external bus cycle and indicates that valid address
information is available on the system address/data bus. ALE differs from ADV#
in that it does not remain active during the entire bus cycle.
An external latch can use this signal to demultiplex the address from the
address/data bus.
On the 8XC196K x , ALE is multiplexed with P5.0, SLPALE, and ADV#.
On the 8XC196J x and 87C196CA, ALE is multiplexed with P5.0 and ADV#.
Analog Ground
ANGND must be connected for A/D converter and port 0 operation. ANGND
and V should be nominally at the same potential.
SS
SIGNAL DESCRIPTIONS
Description
††
, P3.7:0 and PBUS.7:0. AD15:8 are
B-9