Intel 8XC196K Series User Manual page 332

Table of Contents

Figure 13-7 shows the reset-sequence timing. Depending upon when RESET# is brought high,

the CLKOUT signal may become out of phase with the PH1 internal clock. When this occurs, the

clock generator immediately resynchronizes CLKOUT as shown in Case 2.

†Defaults to an 8-bit bus until the CCBs are loaded. AD15:8 strongly drive address during the CCB

†Defaults to an 8-bit bus until the CCBs are loaded. AD15:8 weakly drive address during the CCB fetches.

fetches. For 16-bit systems, write 20H to the high byte of CCB0 and CCB1 (2019H and 201BH) in

For 16-bit systems, write 20H to the high byte of CCB0 and CCB1 (2019H and 201BH) in order to prevent

order to prevent bus contention.

bus contention.

The following events will reset the device (see Figure 13-8):

an external device pulls the RESET# pin low

the CPU issues the reset (RST) instruction

the CPU issues an idle/powerdown (IDLPD) instruction with an illegal key operand

the watchdog timer (WDT) overflows

the oscillator fail detect (OFD) circuitry is enabled and an oscillator failure occurs

The following paragraphs describe each of these reset methods in more detail.

Phases Resynchronized

Bus parameters defined by CCB0 (ready

control, bus width, and bus-timing

modes) take effect here.

Figure 13-7. Reset Timing Sequence

MINIMUM HARDWARE CONSIDERATIONS

= ADV# Selected