Bus-Hold Protocol (8Xc196Kq, Kr, Ks, Kt Only) - Intel 8XC196K Series User Manual

15.5 BUS-HOLD PROTOCOL (8XC196KQ, KR, KS, KT ONLY)

The 8XC196Kx device supports a bus-hold protocol that allows external devices to gain control
of the address/data bus. The protocol uses three signals, all of which are port 2 special functions:
HOLD#/P2.5 (hold request), HLDA#/P2.6 (hold acknowledge), and BREQ#/P2.3 (bus request).
When an external device wants to use the device bus, it asserts the HOLD# signal. HOLD# is
sampled while CLKOUT is low. The device responds by releasing the bus and asserting HLDA#.
During this hold time, the address/data bus floats, and signals ALE, RD#, WR#/WRL#,
BHE#/WRH#, and INST are weakly held in their inactive states. Figure 15-8 shows the timing
for bus-hold protocol, and Table 15-3 on page 15-18 lists the timing parameters and their defini-
tions. Refer to the data sheet for timing parameter values.
CLKOUT
HOLD#
HLDA#
BREQ#
Bus
BHE#, INST
RD#, WR#
WRL#, WRH#
ALE
ADV#
T
HVCH
Hold
Latency
T
CLHAL
T
CLBRL
T
HALAZ
T
HALBZ
Weakly Driven Inactive
ADV# weakly driven
Figure 15-8. HOLD#, HLDA# Timing
INTERFACING WITH EXTERNAL MEMORY
T
HVCH
T
CLHAH
T
CLBRH
T
HAHAX
T
HAHBV
Weakly Driven Inactive
T
CLLH
Start of strongly driven ADV# and ALE
A0165-02
15-17