Design Considerations - Intel 8XC196K Series User Manual

8XC196K x , J x , CA USER'S MANUAL
AD_RESULT (Read)
The A/D result (AD_RESULT) register consists of two bytes. The high byte contains the eight most-
significant bits from the A/D converter. The low byte contains the two least-significant bits from a ten-
bit A/D conversion, indicates the A/D channel number that was used for the conversion, and indicates
whether a conversion is currently in progress.
15
ADRLT9 ADRLT8
7
ADRLT1 ADRLT0
Bit Bit
Number Mnemonic
15:6 ADRLT9:0
5:4 —
3 STATUS
2:0 ACH2:0
Figure 11-6. A/D Result (AD_RESULT) Register — Read Format

11.6 DESIGN CONSIDERATIONS

This section describes considerations for the external interface circuitry and describes the errors
that can occur in any A/D converter. The datasheet lists the absolute error specification, which
includes all deviations between the actual conversion process and an ideal converter. However,
because the various components of error are important in many applications, the datasheet also
lists the specific error components. This section describes those components. For additional in-
formation and design techniques, consult AP-406, MCS
number 270365). Application note AP-406 is also included in Automotive Products and Embed-
ded Microcontrollers handbooks.
11-10
ADRLT7 ADRLT6
— —
A/D Result
These bits contain the A/D conversion result.
Reserved. These bits are undefined.
A/D Status
Indicates the status of the A/D converter. Up to 8 state times are required
to set this bit following a start command. When testing this bit, wait at
least the 8 state times.
1 = A/D conversion is in progress
0 = A/D is idle
A/D Channel Number
These bits indicate the A/D channel number that was used for the
conversion. The 87C196CA, 8XC196J x devices have six channel inputs.
These channels are numbered 2–7. The 8XC196K x devices have eight
channels, numbered 0–7.
Reset State:
ADRLT5 ADRLT4
STATUS ACH2
Function
®
96 Analog Acquisition Primer (order
Address: 1FAAH
7F80H
8
ADRLT3 ADRLT2
0
ACH1 ACH0