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Intel Quark SE Series Platform Manual

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Intel® Quark™ SE Microcontroller C1000
Platform Design Guide
June 2017
Document Number: 334715-004EN

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Summary of Contents for Intel Quark SE Series

  • Page 1 Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...
  • Page 2 You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein.

  • Page 3: Table Of Contents

    Signal Descriptions ............................39 Features ................................41 General Purpose I/O (GPIO) ........................42 Signal Descriptions ............................42 Features ................................43 10.0 JTAG ................................44 10.1 Signal Descriptions ............................44 Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...
  • Page 4 Termination of Unused Pins ........................56 14.1 Guidelines for Terminating Unused Pins ..................... 56 14.2 Termination of Unused Pins for Intel® Quark™ SE Microcontroller C1000 ......56 14.2.1 GPIO Pin Termination ........................ 56 14.2.2 Sensor Subsystem SPI Pin Termination ................57 14.2.3...
  • Page 5 32Mhz Crystal Oscillator specification ....................40 Table 22. 32Khz Crystal Oscillator specification ....................41 Table 23. GPIO Signals ..............................42 Table 24. GPIO Pin Routing Guidelines ........................43 Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...
  • Page 6 USB Signals ............................... 48 Table 28. USB Routing Requirements ........................49 Table 29. Timing Parameters for External Regulator ..................53 Table 30. Recommended Termination Methods for Unused Pins ..............61 Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...
  • Page 7  Added reference to HOST_1P8 voltage rail. November 2016  Minor corrections to signal names.  Power delivery and clocking sections updated. July 2016 Initial release. § Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...

  • Page 8: Introduction

    Overview This design guide provides motherboard implementation recommendations for the Intel® Quark™ SE microcontroller C1000 platform, based on the Intel® Quark™ SE microcontroller processor. This document includes design guidelines for Intel® Quark™ SE microcontroller platforms and the hardware integration aspects that must be considered when designing a platform.

  • Page 9: Terminology

    Reference Documents Table 2. Reference Documents Document Document No./Location Intel® Quark™ SE Microcontroller C1000 Datasheet 334712 Intel® Quark™ SE Microcontroller C1000 Power Sequencing 335277 Considerations Application Note § Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...

  • Page 10: System Assumptions

    Intel® Quark™ SE microcontroller C1000 Customer Reference Board (CRB) system topology and interface connectivity. The Intel® Quark™ SE microcontroller C1000 CRB is used as a baseline reference example for guidelines. Figure 1. Intel® Quark™ SE Microcontroller C1000 CRB Block Diagram Intel®...

  • Page 11: Pcb Technology And Stackup

    1 oz. However, the defined trace thickness range allows for significant process variance around this nominal.  Dual stripline is assumed to be built from 1 oz. copper, based on the Intel® Quark™ SE Microcontroller C1000 layout layers 2/3/4/5. Intel® Quark™ SE Microcontroller C1000...

  • Page 12: Figure 3. Single-Ended Microstrip Diagram

    The parameter values for internal and external traces are the final thickness and width after the motherboard materials are laminated, conductors plated, and etched. Intel uses these exact values to generate the associated electrical models for simulation. Figure 3. Single-Ended Microstrip Diagram Figure 4.

  • Page 13: Backward And Forward Coupling Coefficient Calculation

    However, crosstalk level, which is governed by trace spacing, is not implied by the impedance target. In cases where the selected stackup varies from the Intel recommendation, we recommend calculating and comparing the backward coupling coefficient to choose proper trace spacing.

  • Page 14: Feature Set

    A device can contain any feature set and capabilities supported on the Intel® Quark™ SE microcontroller C1000. The following is a feature set of a sample wearable device used in the Intel® Quark™ SE microcontroller C1000 form factor. Refer to the Intel® Quark™ SE Microcontroller C1000 Datasheet for the latest features supported on the platform.

  • Page 15: 2.4 Pin Mapping

    USB power (5V) via debug port 2.4 Pin Mapping The Intel® Quark™ SE microcontroller C1000 has multiple functional modes, and the interfaces and ball mapping are described below. Please refer to guides for BIOS writers to familiarize yourself with the detailed firmware requirements for setting the particular functions.

  • Page 16: Figure 9. Soc Interfaces

    SPI0_M_CS_B[3] Chip Select 3 GPIO[21]/SPI0 Master GPIO[21] SPI0_M_SCK Clock GPIO[18]/I2S Transmit GPIO[18] I2S_TSCK Clock GPIO[13]/SPI1 Master GPIO[13] SPI1_M_CS_B[2] Chip Select 2 GPIO[10]/SPI1 Master GPIO[10] SPI1_M_MOSI Master-Out Slave-In Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...
  • Page 17 [13]/Pulse Width Modulation[3] GPIO[28] GPIO[28] GPIO[22]/SPI0 Master GPIO[22] SPI0_M_MISO Master-In Slave-Out GPIO[19]/I2S Transmit GPIO[19] I2S_TWS Write Select GPIO[15] I2S_RXD GPIO[15]/I2S Receive GPIO[11]/SPI1 Master GPIO[11] SPI1_M_CS_B[0] Chip Select 0 Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...
  • Page 18 Subsystem[15]/ Platform Clock Output 1 GPIO for Sensor GPIO_SS[12] PWM[2] Subsystem[12]/ PWM[2] GPIO[25]/SPI0 Master GPIO[25] SPI0_M_CS_B[1] Chip Select 1 GPIO[24]/ SPI0 Master GPIO[24] SPI0_M_CS_B[0] Chip Select 0 Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...
  • Page 19 UART1_RTS In[9]/UART1 Ready to Send TRST_B JTAG reset JTAG clock JTAG master select JTAG data in 1.8v from platform to VCC_HOST_1P8_PG Ground for Always On VSS_IO_AON Ground Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...
  • Page 20 VCCOUT_AVD_OPM_2P6 supply for OPM Ground sense on VSS_GNDSENSE_ESR2 switching regulator 2 Ground for switching VSS_AVS_ESR2 regulator 2 1.8 supply voltage for VCC_RTC_1P8 VCC_SRAM_1P8 1.8 SRAM supply voltage Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...
  • Page 21 Switching regulator 2 VCC_BATT_ESR3_3P7 Ground Sense for over VSS_GNDSENSE_OPM voltage protection module VSense on Switching VCC_VSENSE_PLAT_1P8 Regulator2 VSense on Switching VCC_VSENSE_PLAT_3P3 Regulator1 VSense on Switching VCC_VSENSE_HOST_1P8 Regulator3 Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...
  • Page 22 Ground Sense for VSS_GNDSENSE_ESR3 switching reg3 3.3 comparators supply VCC_CMP_3P3 voltage VSS_AVSS_CMP Ground for comparators VCC_ADC_3P3 3.3 ADC supply voltage USB_DN USB negative Ground § Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...

  • Page 23: Subsystem Details

    Design Recommendations The Intel® Quark™ SE microcontroller C1000 is an ultra-low-power Intel® architecture SoC that integrates an Intel® Quark™ SE microcontroller processor core, memory subsystem with on-die volatile and non-volatile storage, and I/O interfaces into a single system-on-chip solution.

  • Page 24: General Design Guideline Assumptions

    All routing guidelines in this document are simulated based on the CRB stackup. Note: For technical specifications (such as speeds, supported resolutions, and data rates), Note: please refer to the Intel® Quark™ SE Microcontroller C1000 Datasheet. Table 5. Good Layout Practices Stitching Vias Provide stitching vias for layer transitions.

  • Page 25: I 2 C Interface

    C Interface C is a two-wire serial bus for inter-IC communication. One wire is for data, and the other wire is for clock. The Intel® Quark™ SE microcontroller C1000 has two I controllers, each with its own independent two-wire bus.

  • Page 26: Figure 10. I 2 C Point-To-Point Topology

    Figure 10. I C Point-to-Point Topology The following table shows detailed routing requirements for the I C bus. Table 7. C Point-to-Point Platform Routing Guidelines Leveraged from Intel® Quark™ SoC C (SDA, SCL) Breakout Segment trace Transmission Line Segment Breakoutsoc...

  • Page 27: Table 8. Capacitance Estimates For Calculating Rpu Values

    (Resistance X Capacitance) does not meet the I C rise and fall time specification. Analysis of a particular layout is required to confirm correct operation. § Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...

  • Page 28: Pulse Width Modulation (Pwm)

    The Timer and PWM block supports the generation of PWM Output signals with configurable low and high times, which allows both the duty cycle and frequency to be set. Example PWM Output signals are shown in the following figures. Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...

  • Page 29: Functional Operation

    In Timer Mode, the timeout period can be configured as follows. This assumes a nominal system clock frequency of 32 MHz. The values, in nanoseconds, will differ if the system clock frequency is changed. Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide...

  • Page 30: Table 11. Timer Period

    0 to 134.22 s Timer Mode supports the following maskable interrupt source:  Timer expiry Interrupts are cleared by reading the Timer End of Interrupt register. § Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...

  • Page 31: Uart

    SoC. UART_x_RTS Output UART A Request to send (RS232) UART_x_CTS Input UART A Clear to send (RS232) Figure 14. UART Point-to-Point Topology UART ATP SoC Device UART_TXD/RXD/CTS/RTS Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...

  • Page 32: Features

     Differential driver/receiver is external to the SoC  Driver enable (DE) and Receiver enable (RE) outputs are driven from the SoC to control the differential driver/receiver Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...
  • Page 33  Fraction resolution is 4 bits  Exception: 2.07% error for 1.391 Mbaud, 2.12% for 1.882 Mbaud and 2Mbaud, 2.53% error for 1.684 Mbaud § Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...

  • Page 34: Spi

    The Serial I/O implements two SPI controllers that support master mode and one SPI controller that supports slave mode. Refer to the Intel® Quark™ SE Microcontroller C1000 Datasheet for additional SPI compatibility requirements and features. Support for SPI Flash devices is a key platform requirement and is needed for all SoC designs.

  • Page 35: Figure 16. Spi Point-To-Point Dual Flash Topology

    33Ω Reference VSS referencing W is the trace width Figure 16. SPI Point-to-Point Dual Flash Topology FLASH Device 0 ATP SOC FLASH Dual Load Device 1 MOSI/MISO/SPI_IO/CLK Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...

  • Page 36: Figure 17. Spi_Cs Point-To-Point Dual Flash Topology

    Via stub length < 80 mils 33Ω Reference VSS referencing W is the trace width Figure 17. SPI_CS Point-to-Point Dual Flash Topology ATP SOC FLASH Device Dual Load SPI_CS Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...

  • Page 37: Features

    Two SPI master interfaces  Control of up to four Slave Selects  Frame formats:  Motorola* SPI  Texas Instruments* SSP  National Semiconductor Microwire*  Transfer modes: Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...
  • Page 38 Configurable Clock Polarity and Clock Phase  Hardware Handshake Interface to support DMA capability  Interrupt Control  FIFO mode support with 16B deep TX and RX FIFOs § Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...

  • Page 39: Clocking

    The RTC is powered from the same battery supply as the rest of the SoC and does not have its own dedicated supply. Signal Descriptions Figure 18. RTC Topology Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...

  • Page 40: Table 19. Rtc Signals

    Crystal frequency Cesr Crystal ESR 12.68 14.41 Ω Crystal Motional Cap 3.34 3.54 Crystal Shunt Cap 0.84 Crystal Load Cap Ftol Frequency Tolerance Dlev Drive Level (25Ω) Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...

  • Page 41: Features

    Comparator for Interrupt/Wake Event generation based on the programmed Match Value  Support for Interrupt/Wake Event generation when only the Counter Clock is running (Fabric Clock is off) § Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...

  • Page 42: General Purpose I/O (Gpio)

    There are 16 additional GPIOs available via the Sensor Subsystem. Signal Descriptions Table 23. GPIO Signals Signal Name Direction/Type Description GPIO[31:0] 32 General Purpose IO’s Figure 19. GPIO Pin Routing Topology Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...

  • Page 43: Features

    Interrupt mode supported for all GPIOs, configurable as follows:  Active High Level  Active Low Level  Rising Edge  Falling Edge  Both Edge  Debounce logic for interrupt sources § Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...

  • Page 44: Jtag

    <1100 mil length Length mismatch between <250 mil DATA and TCK Reference VSS referencing Termination R1 = 51 Ω +/- 5%; R2 = 51 Ω +/- 5% Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...

  • Page 45: Features

    The following is a list of the JTAG Interface features:  5-pin IEEE 1149.1 JTAG Interface  Boundary scan support  ARC metaware debugger  LMT minutia debugger § Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...

  • Page 46: Analog-To-Digital Converter (Adc)

     Integral Non-Linearity (INL) = +/- 2.0 LSB  SINAD = 68 dBFS  Offset Error = +/- 2 LSB (calibration enabled), +/- 64 LSB (calibration disabled) Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...
  • Page 47 1 conversion cycle = (resolution bits + 2) cycles  Full-scale input range is 0 to AVDD.  ADC Reference Voltage (Vrefp) of ADC HIP is connected to AVDD. § Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...

  • Page 48: Usb

    USB_PADN USB Negative differential signal USB_VDD3P3 Input USB 3.3V USB_VSS Input USB Ground 12.1 Signal Descriptions Figure 22. USB Topology Figure 23. USB Topology – Block Diagram Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...

  • Page 49: Features

    Buffer mode DMA supported (scatter gather mode is not supported)  DMA control per endpoint per direction supported  Generates DMA interrupt after a configurable number of bytes/packets have been transmitted Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...
  • Page 50 Supports a single FIFO for all OUT end points  The receive FIFO is sized at two maximum sized packets  The receive FIFO can be filled with minimum sized packets § Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...

  • Page 51: Power

    Power 13.0 Power The Intel® Quark™ SE SoC-based platform has the option to use either internal regulators from the SoC or external power sources from the platform. This chapter provides information about how to configure both internal and external voltage regulators (VRs).

  • Page 52: Figure 24. Configuration For External Vr

    VCC_AON_1P8 VCCOUT_QLR2_1P8 1.8V or 3.3V VCCOUT_ESR2_1P8 (from external supply) VSS_GNDSENSE_ESR2 VCC_IO_AON VCC_SENSE_ESR3 1.8V (from external supply) VCCOUT_QLR3_1P8 VCCOUT_ESR3_1P8 VCC_HOST_1p8 VSS_GNDSENSE_ESR3 Figure 25. Power Sequence for External Regulator Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...

  • Page 53: Configuration For Internal Vr

    For 1.8V, leave VCCOUT_PLAT_1P8_1P8. 4. Connect both VSS_GNDSENSE_ESRx signals to reference plane (GND). 5. VCC_IO_AON can use either internal VR or external VR as the power source. Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...

  • Page 54: Figure 27. Power Delivered By An Internal 1.8V Vr Only

    Quark™ SE microcontroller C1000 reference voltage OPM_2P6 is discharged to ground before a power up cycle. For suggestions on how to ensure the correct voltage levels in VCC_AVD_OPM_2P6 at any time, refer to the Intel® Quark™ SE Microcontroller C1000 Power Sequencing Considerations Application Note.

  • Page 55: Figure 28. Power Sequence For Internal Regulator

    Power Figure 28. Power Sequence for Internal Regulator § Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...

  • Page 56: Termination Of Unused Pins

    Pulling down to VSS consumes about 15% less power than pulling up to VCC for CMOS technology based components. The following sections describe the methods of termination recommended for the Intel® Quark™ SE microcontroller C1000, according to the types of unused pins. 14.2 Termination of Unused Pins for Intel® Quark™ SE Microcontroller C1000 The Intel®...

  • Page 57: Sensor Subsystem Spi Pin Termination

    Any other SPI pins could be left unconnected as they initiate as outputs, or they could also be pulled down to VSS to maintain their LOW states during power up cycle. Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide...

  • Page 58: C Pin Termination

    32. This maintains the I C bus in idle state. Figure 31. I C Pin Termination Example Intel® Quark SE Microcontroller C1000 BGA 144 Package 10 kΩ I2C0_SDA Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...

  • Page 59: Uart Pin Termination

    Figure 34 illustrates termination of the JTAG_TCK pin (ball G2), which is connected to VSS through a 10 kΩ pull-down resistor. The JTAG TMS, TRST_B and TDI pins Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...

  • Page 60: Usb Pin Termination

    C1000 BGA 144 Package 10 kΩ USB_DN USB_DP 14.2.7 Pin Termination Summary The following table describes the methods of termination for all interfaces described in this chapter. Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...

  • Page 61: Table 30. Recommended Termination Methods For Unused Pins

    GPIO[19] GPIO[19] 1 - 10 kΩ R to VSS GPIO[15] GPIO[15] 1 - 10 kΩ R to VSS GPIO[11] GPIO[11] 1 - 10 kΩ R to VSS Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...
  • Page 62 1 - 10 kΩ R to VSS GPIO_AON[0] Always On GPIO [0] 1 - 10 kΩ R to VSS GPIO_AON[2] Always On GPIO [2] 1 - 10 kΩ R to VSS Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...
  • Page 63 1 - 10 kΩ R to VSS VCCOUT_AVD_OPM_2P6 2.6 Output voltage supply for OPM VSS_GNDSENSE_ESR2 Ground sense on switching regulator 2 VSS_AVS_ESR2 Ground for switching regulator 2 Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...
  • Page 64 Tied to DN and 1 - 10 kΩ R USB_DP USB positive to VSS VCC_USB_3P3 3.3 supply voltage for USB Ground VCC_BATT_ESR1_3P7 Mains supply voltage for ESR1 Intel® Quark™ SE Microcontroller C1000 Platform Design Guide June 2017 Document Number: 334715-004EN...
  • Page 65 3.3 comparators supply voltage VSS_AVSS_CMP Ground for comparators VCC_ADC_3P3 3.3 ADC supply voltage Tied to DP and 1 - 10 kΩ R USB_DN USB negative to VSS Ground § Intel® Quark™ SE Microcontroller C1000 June 2017 Platform Design Guide Document Number: 334715-004EN...

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