Design Considerations For 87C196Ca Devices - Intel 8XC196K Series User Manual

Chapter 16, "Programming the Nonvolatile Memory," provides recommended circuits, the corre-
sponding memory maps, and flow diagrams. It also provides procedures for auto programming
and describes the commands used for serial port programming.
2.7

DESIGN CONSIDERATIONS FOR 87C196CA DEVICES

Some functions that were implemented on 8XC196Kx devices are omitted from the 87C196CA.
Table 2-3 lists the pins and signals that are omitted.
Table 2-3. Unsupported Functions in 87C196CA Devices
Removed Pins or Signals
P0.0 and P0.1
P1.4/EPA4, P1.5/EPA5, P1.6/EPA6, P1.7/EPA7
P2.3/BREQ, P2.5/HOLD#
P5.1/INST/SLPCS#
SLPINT (multiplexed with P5.4 in K x devices)
P5.7/BUSWIDTH
P6.2/T1CLK, P6.3/T1DIR
Follow these recommendations to help maintain hardware and software compatibility between
the 87C196CA and future devices.
•
Bus width. Since the 87C196CA has no BUSWIDTH pin, the device cannot dynamically
switch between 8- and 16-bit bus widths. Configure the CCBs to select either 8- or 16-bit
bus width.
•
EPA4–EPA7. The 87C196CA has neither the EPA7:4 pins nor the associated functions.
•
Slave port. The 87C196CA has no P5.1/SLPCS# pin and no SLPINT signal, so you cannot
use the slave port.
•
I/O ports. The following port pins do not exist in the 87C196CA: P0.1:0; P1.7:4; P2.3 and
P2.5; P5.1 and P5.7; P6.2 and P6.3. Software can still read the associated Px_DIR,
Px_MODE, and Px_REG registers. The registers for the removed pins are permanently
configured as follows:
— Px_DIR bits are set.
— Px_MODE bits are clear, except P5_MODE.7 is set.
— Px_REG bits are set.
Do not use the bits associated with the removed port pins for conditional branch instruc-
tions. Treat these bits as reserved.
•
Auto programming. During auto programming, the 87C196CA supports only a 16-bit,
zero-wait-state bus configuration.
ARCHITECTURAL OVERVIEW
Unsupported Functions
Analog channels 0 and 1
EPA channels 4 through 7
Bus hold request and hold acknowledge
Instruction fetch indication and slave port
Slave port (P5.4 is implemented as a low-speed I/O pin)
Dynamic buswidth selection
External clocking and direction control of timer 1
2-13