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Intel Agilex Manuals
Manuals and User Guides for Intel Agilex. We have
8
Intel Agilex manuals available for free PDF download: Configuration User Manual, User Manual
Intel Agilex Configuration User Manual (196 pages)
Brand:
Intel
| Category:
Microcontrollers
| Size: 3 MB
Table of Contents
Table of Contents
2
1 Intel ® Agilex ™ Configuration User Guide
5
Intel ® Agilex ™ Configuration Overview
5
Configuration and Related Signals
8
Intel Download Cables Supporting Configuration in Intel Agilex Devices
9
Intel Agilex Configuration Architecture
11
Secure Device Manager
12
2 Intel Agilex Configuration Details
16
Intel Agilex Configuration Timing Diagram
16
Configuration Flow Diagram
20
Reset Release Intel FPGA IP
23
Additional Clock Requirements for HPS, Pcie, and HBM2
25
Intel Agilex Configuration Pins
25
SDM Pin Mapping
26
MSEL Settings
27
Device Configuration Pins for Optional Configuration Signals
28
Configuration Clocks
38
Setting Configuration Clock Source
38
OSC_CLK_1 Clock Input
39
3 Intel Agilex Configuration Schemes
41
Avalon-ST Configuration
41
Avalon-ST Configuration Scheme Hardware Components and File Types
43
Enabling Avalon-ST Device Configuration
44
The AVST_READY Signal
45
RBF Configuration File Format
48
Avalon-ST Single-Device Configuration
49
Debugging Guidelines for the Avalon-ST Configuration Scheme
52
QSF Assignments for Avalon-ST X8
53
QSF Assignments for Avalon-ST X16
55
QSF Assignments for Avalon-ST X32
57
IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
59
AS Configuration
86
AS Configuration Scheme Hardware Components and File Types
88
AS Single-Device Configuration
90
AS Using Multiple Serial Flash Devices
91
AS Configuration Timing Parameters
93
Maximum Allowable External AS_DATA Pin Skew Delay Guidelines
94
Programming Serial Flash Devices
95
Serial Flash Memory Layout
99
As_Clk
100
Active Serial Configuration Software Settings
101
Intel Quartus Prime Programming Steps
102
Debugging Guidelines for the as Configuration Scheme
106
QSF Assignments for as
108
SD/MMC Configuration
111
SD/MMC Single-Device Configuration
112
JTAG Configuration
113
JTAG Configuration Scheme Hardware Components and File Types
114
JTAG Device Configuration
115
JTAG Multi-Device Configuration
118
Debugging Guidelines for the JTAG Configuration Scheme
119
4 Remote System Update (RSU)
121
Remote System Update Functional Description
123
Remote System Update Using as Configuration
124
Remote System Update Configuration Images
125
Remote System Update Configuration Sequence
126
RSU Recovery from Corrupted Images
127
Updates with the Factory Update Image
130
Guidelines for Performing Remote System Update Functions for Non-HPS
131
Commands and Responses
132
Operation Commands
134
Error Code Responses
140
Quad SPI Flash Layout
141
Detailed Quad SPI Flash Layout
146
Generating Remote System Update Image Files Using the Programming File Generator
151
Generating an Application Image
153
Generating a Factory Update Image
155
Remote System Update from FPGA Core Example
159
Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
161
Programming Flash Memory with the Initial Remote System Update Image
167
Reconfiguring the Device with an Application or Factory Image
171
Adding an Application Image
172
Removing an Application Image
177
5 Intel Agilex Configuration Features
180
Partial Reconfiguration
182
6 Intel Agilex Debugging Guide
183
Intel Agilex Configuration Architecture Overview
184
Configuration File Format Differences
185
Understanding Seus
186
Understanding and Troubleshooting Configuration Pin Behavior
187
Nconfig
188
CONF_DONE and INIT_DONE
189
SDM_IO Pins
190
7 Intel Agilex Configuration User Guide Archives
193
8 Document Revision History for the Intel Agilex Configuration User Guide
194
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Intel Agilex Configuration User Manual (108 pages)
Brand:
Intel
| Category:
Microcontrollers
| Size: 0 MB
Table of Contents
Table of Contents
2
1 Intel ® Agilex ™ Configuration Overview
5
Configuration and Related Signals
8
Intel Download Cables Supporting Configuration in Intel Agilex Devices
9
Intel Agilex Configuration Architecture
10
Secure Device Manager
11
2 Intel Agilex Configuration Details
14
Intel Agilex Configuration Timing Diagram
14
Configuration Flow Diagram
17
Intel Agilex Reset Release IP
19
Additional Clock Requirements for Transceivers, HPS, Pcie, and EMIF
21
Intel Agilex Configuration Pins
22
SDM Pin Mapping
22
MSEL Settings
27
Device Configuration Pins
28
Configuration Clocks
32
OSC_CLK_1 Clock Input
32
3 Intel Agilex Configuration Schemes
34
Avalon-ST Configuration
34
Avalon-ST Configuration Scheme Hardware Components and File Types
35
The AVST_READY Signal
36
RBF Configuration File Format
39
Avalon-ST Single-Device Configuration
40
Debugging Guidelines for the Avalon-ST Configuration Scheme
43
IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
44
AS Configuration
53
AS Configuration Scheme Hardware Components and File Types
54
AS Single-Device Configuration
56
AS Using Multiple Serial Flash Devices
57
AS Configuration Timing Parameters
59
Maximum Allowable External AS_DATA Pin Skew Delay Guidelines
59
Programming Serial Flash Devices
60
Serial Flash Memory Layout
64
As_Clk
65
Debugging Guidelines for the as Configuration Scheme
66
Configuration from SD/MMC
68
SD/MMC Single-Device Configuration
69
JTAG Configuration
70
JTAG Configuration Scheme Hardware Components and File Types
71
JTAG Device Configuration
72
JTAG Multi-Device Configuration
74
Debugging Guidelines for the JTAG Configuration Scheme
76
4 Intel Agilex Configuration Features
78
Device Security
78
Configuration Via Protocol
78
Partial Reconfiguration
80
5 Remote System Update
81
Remote System Update Functional Description
83
Remote System Update Using as Configuration
83
Remote System Update Configuration Images
84
Remote System Update Configuration Sequence
85
RSU Recovery from Corrupted Images
86
Update of Static Firmware and Factory Image
88
Guidelines for Performing Remote System Update Functions for Non-HPS
89
Commands and Responses
90
Operation Commands
92
Error Code Responses
96
Remote System Update Flash Device Layout
97
Configuration Firmware Pointer Block (CPB)
98
6 Intel Agilex Debugging Guide
99
Configuration Debugging Checklist
99
Intel Agilex Configuration Architecture Overview
100
Configuration Pin Differences from Previous Device Families
101
Configuration File Format Differences
103
Understanding Seus
104
Reading the Unique 64-Bit CHIP ID
104
Understanding and Troubleshooting Configuration Pin Behavior
104
Nconfig
105
Nstatus
106
CONF_DONE and INIT_DONE
107
7 Document Revision History for the Intel Agilex Configuration User Guide
108
Intel Agilex User Manual (56 pages)
General Purpose I/O and LVDS SERDES
Brand:
Intel
| Category:
Microcontrollers
| Size: 0 MB
Table of Contents
Table of Contents
2
1 Intel ® Agilex ™ General Purpose I/O and LVDS SERDES Overview
4
Intel Agilex I/O and Differential I/O Buffers
4
Package Selection and I/O Vertical Migration Support
5
I/O Banks
5
2 Intel Agilex I/O Features and Usage
8
GPIO Features
8
Supported I/O Standards
8
Intel Agilex I/O Buffer Behavior
10
I/O Standards Restrictions and Implementation Guidelines
10
Programmable I/O Element (IOE) Features in Intel Agilex Devices
11
Programmable Output Slew Rate Control
15
Programmable IOE Delay
15
Programmable Open-Drain Output
15
Programmable Bus Hold
16
Programmable Pull-Up Resistor
16
Programmable Pre-Emphasis
16
Programmable De-Emphasis
17
Programmable Differential Output Voltage
18
3 Intel Agilex I/O Termination
19
True Differential Signaling I/O Termination
19
External I/O Termination
20
True Differential Signaling I/O Standard OCT Termination
20
Single-Ended I/O Termination in Intel Agilex Devices
21
Single-Ended I/O Standard OCT Termination
21
OCT Calibration Block
25
Single-Ended I/O Standards External Termination
26
4 Intel Agilex I/O Design Guidelines
29
Placement Requirements
29
Special Pins Requirement
29
External Memory Interface Pin Placement Requirements
30
HPS Shared I/O Requirements
31
SDM Shared I/O Requirements
31
Configuration Pins
31
Unused Pins
31
Guidelines for GPIO Pins During Power Sequencing
32
Maximum DC Current Restrictions
32
I/O Interface Voltage Level Compatibility
32
I/O Simulation
34
HSPICE Models
34
5 Intel Agilex High-Speed SERDES I/O Architecture
35
Intel Agilex High-Speed SERDES I/O Overview
35
High-Speed SERDES Architecture
35
Intel Agilex GPIO Banks, SERDES, and DPA Locations
38
Intel Agilex LVDS SERDES Transmitter
39
LVDS SERDES Transmitter Blocks
39
Serializer Bypass for DDR and SDR Operations
39
Serializer
40
Differential I/O Bit Position
41
Clocking Differential Transmitters
42
Intel Agilex LVDS SERDES Receiver
42
LVDS SERDES Receiver Blocks
42
Clocking LVDS SERDES Receivers
47
LVDS SERDES Receiver Modes
47
Intel Agilex LVDS SERDES Source-Synchronous Timing Budget
50
Transmitter Channel-To-Channel Skew
50
Receiver Skew Margin
51
Intel Agilex LVDS SERDES Timing
52
I/O Timing Analysis
53
Intel Agilex LVDS SERDES Design Guidelines
53
Use High-Speed Clock from PLL to Clock SERDES Only
53
Pin Placement for Differential Channels
54
SERDES Pin Pairs for Soft-CDR Mode
54
6 Documentation Related to the Intel Agilex General Purpose I/O and LVDS SERDES User Guide
55
7 Document Revision History for the Intel Agilex General Purpose I/O and LVDS SERDES User Guide
56
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Intel Agilex User Manual (73 pages)
Variable Precision DSP Blocks
Brand:
Intel
| Category:
Microcontrollers
| Size: 0 MB
Table of Contents
Table of Contents
2
1 Intel ® Agilex ™ Variable Precision DSP Blocks Overview
4
Features
4
Supported Operational Modes in Intel Agilex Devices
5
Fixed-Point Arithmetic
5
Floating-Point Arithmetic
7
2 Intel Agilex Variable Precision DSP Blocks Architecture
9
Fixed-Point Arithmetic
12
Input Register Bank for Fixed-Point Arithmetic
12
Pipeline Registers for Fixed-Point Arithmetic
16
Pre-Adder for Fixed-Point Arithmetic
17
Internal Coefficient for Fixed-Point Arithmetic
17
Multipliers for Fixed-Point Arithmetic
17
Adder or Subtractor for Fixed-Point Arithmetic
17
Accumulator, Chainout Adder, and Preload Constant for Fixed-Point Arithmetic
18
Systolic Register for Fixed-Point Arithmetic
19
Double Accumulation Register for Fixed-Point Arithmetic
19
Output Register Bank for Fixed-Point Arithmetic
20
Floating-Point Arithmetic
20
Input Register Bank for Floating-Point Arithmetic
20
Pipeline Registers for Floating-Point Arithmetic
22
Multipliers for Floating-Point Arithmetic
23
Adder or Subtractor for Floating-Point Arithmetic
24
Output Register Bank for Floating-Point Arithmetic
24
Exception Handling for Floating-Point Arithmetic
25
3 Intel Agilex Variable Precision DSP Blocks Operational Modes
32
Operational Modes for Fixed-Point Arithmetic
32
Independent Multiplier Mode
32
X 8 (Unsigned) or 9 X 9 (Signed) Sum of 4 Mode
34
Multiplier Adder Sum Mode
34
Independent Complex Multiplier
35
Systolic FIR Mode
37
Operational Modes for Floating-Point Arithmetic
40
FP32 Single-Precision Floating-Point Arithmetic Functions
40
FP16 Half-Precision Floating-Point Arithmetic Functions
44
Multiple Floating-Point Variable DSP Blocks Functions
55
4 Intel Agilex Variable Precision DSP Blocks Design Considerations
62
Fixed-Point Arithmetic
62
Configurations for Input, Pipeline, and Output Registers
62
Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic
64
Accumulator for Fixed-Point Arithmetic
64
Input Cascade for Fixed-Point Arithmetic
64
Chainout Adder
67
Floating-Point Arithmetic
67
Configurations for Input, Pipeline, and Output Registers
67
Chainout Adder
72
Guide
73
Intel Agilex User Manual (36 pages)
Embedded Memory
Brand:
Intel
| Category:
Microcontrollers
| Size: 0 MB
Table of Contents
Table of Contents
2
1 Intel ® Agilex ™ Embedded Memory Overview
3
Intel Agilex Embedded Memory Features
3
2 Intel Agilex Embedded Memory Architecture and Features
6
Byte Enable in Intel Agilex Embedded Memory Blocks
6
Byte Enable Controls
6
Data Byte Output
7
Byte Enable Behavior
8
Address Clock Enable Support
8
Asynchronous Clear and Synchronous Clear
10
Memory Blocks Error Correction Code Support
12
Parity Bit
13
ECC Parity Flip
13
ECC Read-During-Write Behavior
13
Error Correction Code Truth Table
14
Intel Agilex Embedded Memory Clocking Modes
14
Single Clock Mode
15
Read/Write Clock Mode
15
Input/Output Clock Mode
15
Asynchronous/Synchronous Clears in Clocking Modes
15
Output Read Data in Simultaneous Read/Write
16
Independent Clock Enables in Clocking Modes
16
Intel Agilex Embedded Memory Configurations
16
Mixed-Width Port Configurations
16
Force-To-Zero
17
Coherent Read Memory
17
Forwarding Logic
20
Freeze Logic
22
True Dual Port Dual Clock Emulator
22
Initial Value of Read and Write Address Registers
26
3 Intel Agilex Embedded Memory Design Considerations
27
Consider the Memory Block Selection
27
Consider the Concurrent Read Behavior
27
Customize Read-During-Write Behavior
28
Same-Port Read-During-Write Mode
28
Mixed-Port Read-During-Write Mode
29
Consider Power-Up State and Memory Initialization
33
Reduce Power Consumption
34
Advanced Settings in Intel Quartus Prime Software for Memory
34
4 Intel Agilex Embedded Memory Debugging
35
5 Document Revision History for the Intel Agilex Embedded Memory User Guide
36
Intel Agilex User Manual (28 pages)
Power Management
Brand:
Intel
| Category:
Microcontrollers
| Size: 0 MB
Table of Contents
Table of Contents
2
1 Intel ® Agilex ™ Power Management Overview
3
Power System Design Phases
3
Choosing a Power Tree
3
Power Estimation
3
Power Optimization
4
Power Generation
4
Power Distribution
4
Power Dissipation and Thermal Considerations
4
Power Supplies
4
2 Intel Agilex Power Basics
5
Power Consumption
5
Power Estimation Basics
5
Early Power Estimator (EPE)
6
Power Analyzer
7
3 Intel Agilex Power and I/O State Sequencing
8
Overview
8
Power-Up Sequence Requirements
8
Power-On Reset
10
Power Supplies Monitored by the por Circuitry
11
4 Intel Agilex Sensor Monitoring System
12
Voltage Monitoring System
12
Voltage Sensor Transfer Function
12
Temperature Monitoring System
13
Local Temperature Sensor
13
Remote Temperature Sensing Diode
14
Temperature Sensor Channels and Locations
15
Intel Agilex Sensors Design Considerations
15
Intel Agilex Voltage Monitor Design Guidelines
15
Intel Agilex Temperature Monitor Design Guidelines
16
5 Intel Agilex Power Optimization Techniques and Features
17
Smartvid Standard Power Devices
17
Smartvid Feature Implementation in Intel Agilex Devices
18
SDM Power Manager
19
Temperature Compensation
23
Intel Agilex Power Management and VID Implementation Guide
24
DSP and M20K Power Gating
26
Clock Gating
26
Power Sense Line
27
Power Optimization Techniques in the Intel Quartus Prime Software
27
6 Document Revision History for the Intel Agilex Power Management User Guide
28
Intel Agilex User Manual (29 pages)
Clocking and PLL
Brand:
Intel
| Category:
Microcontrollers
| Size: 0 MB
Table of Contents
Table of Contents
2
1 Intel ® Agilex ™ Clocking and PLL Overview
3
Clock Networks Overview
3
Plls Overview
3
2 Intel Agilex Clocking and PLL Architecture and Features
4
Clock Networks Architecture and Features
4
Clock Network Architecture
4
Clock Resources
6
Clock Control Features
6
Plls Architecture and Features
9
PLL Features
9
PLL Usage
10
PLL Locations
10
PLL Architecture
11
PLL Control Signals
11
PLL Feedback Modes
12
Clock Multiplication and Division
17
Programmable Phase Shift
18
Programmable Duty Cycle
18
PLL Cascading
18
PLL Input Clock Switchover
19
PLL Reconfiguration and Dynamic Phase Shift
24
PLL Calibration
24
3 Intel Agilex Clocking and PLL Design Considerations
26
Guideline: Clock Switchover
26
Guideline: Timing Closure
27
Guideline: Resetting the PLL
27
Guideline: Configuration Constraints
28
4 Document Revision History for the Intel Agilex Clocking and PLL User Guide
29
Intel Agilex User Manual (20 pages)
Logic Array Blocks and Adaptive Logic Modules
Brand:
Intel
| Category:
Microcontrollers
| Size: 0 MB
Table of Contents
Table of Contents
2
1 Intel ® Agilex ™ LAB and ALM Overview
3
2 Intel Hyperflex ™ Register
4
3 Intel Agilex LAB and ALM Architecture and Features
5
Lab
5
Mlab
6
Local and Direct Link Interconnects
6
Carry Chain Interconnects
7
LAB Control Signals
8
Alm
9
ALM Resources
9
ALM Output
10
ALM Operating Modes
11
4 Document Revision History for the Intel Agilex Logic Array Blocks and Adaptive Logic Modules User Guide
20
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