Intel 8XC196K Series User Manual page 16

Figure
12-11 CAN Message 15 Mask (CAN_MSK15) Register.....................................................12-20
CAN Message Object x Configuration (CAN_MSGxCFG) Register.........................12-21
12-12
12-13 CAN Message Object x Identifier (CAN_MSG x ID0–3) Register ..............................12-22
12-14 CAN Message Object x Control 0 (CAN_MSGxCON0) Register .............................12-24
12-15 CAN Message Object x Control 1 (CAN_MSG x CON1) Register .............................12-26
12-16 CAN Message Object Data (CAN_MSG x DATA0–7) Registers................................12-28
12-17 CAN Control (CAN_CON) Register ..........................................................................12-29
CAN Message Object x Control 0 (CAN_MSGxCON0) Register .............................12-31
12-18
12-19 CAN Interrupt Pending (CAN_INT) Register ............................................................12-32
12-20 CAN Status (CAN_STAT) Register ..........................................................................12-33
CAN Message Object x Control 0 (CAN_MSG x CON0) Register .............................12-34
12-21
12-22 Receiving a Message for Message Objects 1–14 — CPU Flow ..............................12-36
12-23 Receiving a Message for Message Object 15 — CPU Flow ....................................12-37
12-24 Receiving a Message — CAN Controller Flow.........................................................12-38
12-25 Transmitting a Message — CPU Flow .....................................................................12-39
12-26 Transmitting a Message — CAN Controller Flow.....................................................12-40
13-1 Minimum Hardware Connections ...............................................................................13-3
13-2 Power and Return Connections .................................................................................13-4
13-3 On-chip Oscillator Circuit............................................................................................13-6
13-4 External Crystal Connections .....................................................................................13-7
13-5 External Clock Connections .......................................................................................13-8
13-6 External Clock Drive Waveforms................................................................................13-8
13-7 Reset Timing Sequence .............................................................................................13-9
13-8 Internal Reset Circuitry .............................................................................................13-10
13-9 Minimum Reset Circuit .............................................................................................13-11
13-10 Example System Reset Circuit .................................................................................13-11
14-1 Clock Control During Power-saving Modes................................................................14-3
14-2 Power-up and Powerdown Sequence When Using an External Interrupt ..................14-6
14-3 External RC Circuit.....................................................................................................14-7
14-4 Typical Voltage on the V
15-1 Chip Configuration 0 (CCR0) Register .......................................................................15-5
15-2 Chip Configuration 1 (CCR1) Register .......................................................................15-7
15-3 Multiplexing and Bus Width Options...........................................................................15-9
15-4 BUSWIDTH Timing Diagram ....................................................................................15-10
15-5 Timings for 16-bit Buses...........................................................................................15-12
15-6 Timings for 8-bit Buses.............................................................................................15-14
15-7 READY Timing Diagram...........................................................................................15-16
15-8 HOLD#, HLDA# Timing ............................................................................................15-17
15-9 Standard Bus Control ...............................................................................................15-21
15-10 Decoding WRL# and WRH#.....................................................................................15-21
15-11 8-bit System with Flash and RAM ............................................................................15-22
15-12 16-bit System with Dynamic Bus Width....................................................................15-23
15-13 Write Strobe Mode ...................................................................................................15-24
15-14 16-bit System with Single-byte Writes to RAM .........................................................15-25
FIGURES
Pin While Exiting Powerdown.........................................14-8
PP
CONTENTS
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