Intel 8XC196K Series User Manual page 370

Table of Contents

When the device is configured to use a 16-bit bus, separate low- and high-byte write signals must

be generated for single-byte writes. Figure 15-10 shows a sample circuit that combines BHE# and

AD0 to produce these signals (WRL# and WRH#). A similar pair of signals for read is unneces-

sary. For a single-byte read with the 16-bit bus, both bytes are placed on the data bus and the pro-

cessor discards the unwanted byte.

16-bit Bus Cycle

Figure 15-9. Standard Bus Control

Figure 15-10. Decoding WRL# and WRH#

INTERFACING WITH EXTERNAL MEMORY

Address High

8-bit Bus Cycle