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After reset and until CCB1 is read, the bus controller always inserts three wait states into bus cy-
cles. Then, until P5.6 has been configured to operate as the READY signal, the internal ready
control bits (IRC2:0) control the wait states. If IRC2:0 are all set during CCB0 and CCB1 fetch,
READY (P5.6) is configured as a special-function input. If port 5 is initialized after reset, you
must ensure that P5.6 remains configured as the READY input. If P5.6 is configured as a port
pin, the READY input to the device is equal to zero. This will cause an infinite number of wait
states to be inserted into bus cycles and the chip to lock up.
After the CCB1 fetch, the internal ready control circuitry allows slow external memory devices
to increase the length of the read and write bus cycles. If the external memory device is not ready
for access, it pulls the READY signal low and holds it low until it is ready to complete the oper-
ation, at which time it releases READY. While READY is low, the bus controller inserts wait
states into the bus cycle.
The internal ready control bits (IRC2:0) define the maximum number of wait states that will be
inserted. (The IRC2:0 bits are defined in Figures 15-1 and 15-2.) When all three bits are set, the
bus controller inserts wait states until the external memory device releases the READY signal.
Otherwise, the bus controller inserts wait states until either the external memory device releases
the READY signal or the number of wait states equals the number (0, 1, 2, or 3) specified by the
CCB bit settings.
When selecting infinite wait states, be sure to add external hardware to count wait states and re-
lease READY within a specified period of time. Otherwise, a defective external device could tie
up the address/data bus indefinitely.
Ready control is valid only for external memory; you cannot add wait states
when accessing internal ROM.
Setup and hold timings must be met when using the READY signal to insert wait states into a bus
cycle (see Table 15-2 and Figure 15-7). Because a decoded, valid address is used to generate the
READY signal, the setup time is specified relative to the address being valid. This specification,
T
, indicates how much time one has to decode the address and assert READY after the ad-
AVYV
dress is valid. The READY signal must be held valid until the T
Typically, this is a minimum of 0 ns from the time CLKOUT goes low. Do not exceed the maxi-
mum T
specification or additional (unwanted) wait states might be added. In all cases, refer
CLYX
to the data sheets for the current specifications for T
INTERFACING WITH EXTERNAL MEMORY
NOTE
CLYX
and T
AVYV
CLYX
timing specification is met.
.
15-15
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