Intel Max 10 Spi Bus; Clock Circuits - Intel Agilex F Series User Manual

A. Development Kit Components
739942 | 2022.09.21
A.7. Intel MAX 10 SPI Bus
The Intel MAX 10 device uses the SPI bus for reading telemetry information from the
Analog Devices LTC3888 VCC core controller.
Table 39. SPI Signals
Schematic Signal Name
LTC_1V8_SDI
LTC_1V8_SCK
LTC_1V8_SPI_ERRn
LTC_1V8_SCSn
A.8. Clock Circuits
Figure 26. Intel Agilex F-Series FPGA Development Kit Clocks and Default Frequencies
CXL
Conn
(J9)
25 MHz
Y1
PCIe
Gold
Finger
(J1)
Send Feedback
FPGA Pin Number
L2
N2
M1
P1
clk_CXL_conn_P/N (100 MHz)
Refclk_CXL_RP_P/N (100 MHz)
Si52204
Clk_CXL_EP_P/N (100 MHz)
(U25)
Refclk_PCIe_EP_P/N (100 MHz)
Refclk_PCIe_EP_EDGE_P/N (100 MHz)
Intel
I/O Standard
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
PPS_FPGA_clkout
ToD_master_clk_125M_P/N (125 MHz)
clk_FPGA_100M_P/N (100 MHz)
PTP_sample_clk_250M_P/N (250 MHz)
ZL30733
DDR4_DIMM1_refclk_P/N (166.625 MHz)
IEEE
DDR4_DIMM2_refclk_P/N (166.625 MHz)
1588
DDR4_comp_refclk_P/N (166.625 MHz)
Clock
(U23)
QSFPDD_refclk_P/N (156.25 MHz)
QSFP_refclk_P/N (156.25 MHz)
CIPRI_high_P/N (184.32 MHz)
CIPRI_low_P/N (153.6 MHz)
FPGA_rcvd_clk1_REFOUT_P/N
FPGA_rcvd_clk2_REFOUT_P/N
1
Refclk_CXL_conn_P/N
Si53254A
(U27)
Refclk_CXL_EP_P/N
2
OSC
FPGA_OSC_clk1
125 MHz
2
Refclk_PCIe_13A_ch2_P/N
Si53254A
(U26)
Refclk_PCIe_13A_ch5_P/N
1
® ™
Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide
Description
SPI data
SPI clock
SPI error status
SPI chip select
Bank3A
Bank2C
Bank2F
Bank3D
Agilex
Bank12C
FPGA
(U8)
SDM
Bank13A
63