Enabling The Bus-Hold Protocol - Intel 8XC196NT User Manual

Table 14-4. HOLD#, HLDA# Timing Definitions (Continued)
Symbol
T
HAHAX
T
HALBZ
T
HAHBV
T
CLLH
When the external device is finished with the bus, it relinquishes control by driving HOLD# high.
In response, the 8XC196NT drives HLDA# high and assumes control of the bus.
If the 8XC196NT has a pending external bus cycle while it is in hold, it asserts BREQ# to request
control of the bus. After the external device responds by driving HOLD# high, the 8XC196NT
exits hold and then deasserts BREQ# and HLDA#.
If the 8XC196NT receives an interrupt request while it is in hold, the
8XC196NT asserts INTOUT# only if it is executing from internal memory. If
the 8XC196NT needs to access external memory, it asserts BREQ# and waits
until the external device deasserts HOLD# to assert INTOUT#. If the
8XC196NT receives an interrupt request as it is going into hold (between the
time that an external device asserts HOLD# and the time that the 8XC196NT
responds with HLDA#), the 8XC196NT asserts HLDA# and INTOUT# and
waits until the external device deasserts HOLD# to deassert HLDA# and
INTOUT#.

14.6.1 Enabling the Bus-hold Protocol

To use the bus-hold protocol, you must configure P2.3/BREQ#, P2.5/HOLD#, and P2.6/HLDA#
to operate as special-function signals. BREQ# and HLDA# are active-low outputs; HOLD# is an
active-low input.
You must also set the hold enable bit (HLDEN) in the window selection register (WSR.7) to en-
able the bus-hold protocol. Once the bus-hold protocol has been selected, the port functions of
P2.3, P2.5, and P2.6 cannot be selected without resetting the device. (During the time that the pins
are configured to operate as special-function signals, their special-function values can be read
from the P2_PIN.x bits.) However, the hold function can be dynamically enabled and disabled as
described in "Disabling the Bus-hold Protocol."
Parameter
HLDA# High to Address No Longer Float
HLDA# Low to BHE#, INST, RD#, WR#, WRL#, WRH#
Weakly Driven
HLDA# High to BHE#, INST, RD#, WR#, WRL#, WRH# valid
Clock Falling to ALE Rising; Use to derive other timings.
NOTE
INTERFACING WITH EXTERNAL MEMORY
14-21