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Intel 80C196KB Series User Manual

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80C196KB
User's Guide
November 1990
Order Number 270651-003

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Summary of Contents for Intel 80C196KB Series

  • Page 1 80C196KB User’s Guide November 1990 Order Number 270651-003...
  • Page 2 Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel’s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to...

  • Page 3: Table Of Contents

    80C196KB USER’S GUIDE CONTENTS CONTENTS PAGE PAGE 1 0 CPU OPERATION 6 0 Pulse Width Modulation Output (D A) 1 1 Memory Controller 6 1 Analog Outputs 1 2 CPU Control 1 3 Internal Timing 7 0 TIMERS 7 1 Timer1 2 0 MEMORY SPACE 7 2 Timer2 2 1 Register File...
  • Page 4 80C196KB USER’S GUIDE CONTENTS CONTENTS PAGE PAGE 12 0 I O PORTS 15 0 EXTERNAL MEMORY INTERFACING 12 1 Input Ports 15 1 Bus Operation 12 2 Quasi-Bidirectional Ports 15 2 Chip Configuration Register 12 3 Output Ports 15 3 Bus Width 12 4 Ports 3 and 4 AD0–...

  • Page 5: 0 Cpu Operation

    80C196KB USER’S GUIDE The 80C196KB family is a CHMOS branch of the There are many members of the 80C196KB family so MCS -96 family Other members of the MCS-96 fami- to provide easier reading this manual will refer to the ly include the 8096BH and 8098 All of the MCS-96 80C196KB family generically as the 80C196KB components share a common instruction set and archi-...

  • Page 6: 1 Memory Controller

    80C196KB USER’S GUIDE The CPU on the 80C196KB is 16 bits wide and con- REGISTER ALU (RALU) nects to the interrupt controller and the memory con- troller by a 16-bit bus In addition there is an 8-bit bus Most calculations performed by the 80C196KB take which transfers instruction bytes from the memory con- place in the RALU The RALU shown in Figure 1-2 troller to the CPU An extension of the 16-bit bus con-...
  • Page 7 80C196KB USER’S GUIDE Figure 1-2 RALU and Memory Controller Block Diagram...

  • Page 8: 0 Memory Space

    0FFH is made the instructions will be fetched from external memory This section of external memo- ry is reserved for use by Intel development tools The internal RAM from location 018H (24 decimal) to 0FFH is the Register File It contains 232 bytes of RAM which can be accessed as bytes (8 bits) words 270651 –3...
  • Page 9 80C196KB USER’S GUIDE Listed registers are present in all three windows INT MASK1 PEND1 INT MASK1 PEND1 INT MASK1 PEND1 TIMER2 T2 CAPTURE T2 CAPTURE INT MASK PEND INT MASK PEND INT MASK PEND ZERO REG ZERO REG ZERO REG READ WRITE PROGRAMMING WRITE READ...
  • Page 10 80C196KB USER’S GUIDE Register Description Zero Register - Always reads as a zero useful for a base when indexing and as a constant for calculations and compares AD RESULT A D Result Hi Low - Low and high order results of the A D converter AD COMMAND A D Command Register - Controls the A D HSI MODE...
  • Page 11 80C196KB USER’S GUIDE Programming control and test operations are done in in Window 15 (Timer2 was read-only on the 8096 ) Window 14 Registers in this window that are not la- Registers which can be read and written in Window 0 beled should be considered reserved and should not be can also be read and written in Window 15 either read or written...

  • Page 12: 3 Reserved Memory Spaces

    ROMless devices 207FH including those marked ‘‘Reserved’’ are re- served by Intel for use in testing or future products Instruction and data fetches from the internal ROM or They must be filled with the Hex value FFH to insure...

  • Page 13: 5 System Bus

    65536 Logi- MCS -96 MACRO ASSEMBLER USER’S GUIDE cal operations on WORDS are applied bitwise Bits Order Number 122048 (Intel Systems) within words are labeled from 0 to 15 with 0 being the Order Number 122351 (DOS Systems)

  • Page 14: 2 Operand Addressing

    WORD operations For consist- register is selected by an 8-bit field within the instruc- ency with Intel provided software the user should adopt tion and the register address must conform to the oper- the conventions for addressing DOUBLE-WORD op- and type’s alignment rules Depending on the instruc-...
  • Page 15 80C196KB USER’S GUIDE INDIRECT REFERENCES The indirect mode is used to access an operand by plac- file The register which contains the indirect address is ing its address in a WORD variable in the register file selected by an eight bit field within the instruction An The calculated address must conform to the alignment instruction can contain only one indirect reference and rules for the operand type Note that the indirect ad-...

  • Page 16: 3 Program Status Word

    80C196KB USER’S GUIDE LONG-INDEXED REFERENCES This addressing mode is like the short-indexed mode struction can contain only one long-indexed reference except that a 16-bit field is taken from the instruction and the remaining operand(s) must be register-direct and added to the WORD variable to form the address references of the operand No sign extension is necessary An in- Examples...
  • Page 17 80C196KB USER’S GUIDE VT The oVerflow Trap flag is set when the V flag is CONDITION FLAGS set but it is only cleared by the CLRVT JVT and The PSW bits on the 80C196KB are set as follows JNVT instructions The operation of the VT flag allows for the testing for a possible overflow con- dition at the end of a sequence of related arithme- tic operations This is normally more efficient...

  • Page 18: 4 Instruction Set

    80C196KB USER’S GUIDE WORDS can be converted to DOUBLE-WORDS by INTERRUPT FLAGS simply clearing the upper WORD of the DOUBLE- The lower eight bits of the PSW individually mask the WORD (CLR) and INTEGERS can be converted to lowest 8 sources of interrupt to the 80C196KB These LONGS with the EXT (sign extend) instruction mask bits can be accessed as an eight bit byte (INT MASK address 8) in the on-board register file A sep-...
  • Page 19 80C196KB USER’S GUIDE Table 3-1A Instruction Summary Flags Mnemonic Operands Operation (Note 1) Notes VT ST ADD ADDB ADD ADDB ADDC ADDCB SUB SUBB SUB SUBB SUBC SUBCB CMP CMPB MUL MULU MUL MULU MULB MULUB MULB MULUB DIVU (D D 2) A D remainder DIVUB...
  • Page 20 80C196KB USER’S GUIDE Table 3-1B Instruction Summary Flags Mnemonic Operands Operation (Note 1) Notes Z N C V VT ST (SP) SP b b b b b J (conditional) 8-bit offset (if taken) b b b b b Jump if C b b b b b jump if C b b b b b...
  • Page 21 80C196KB USER’S GUIDE Table 3-1C Instruction Summary Flags Mnemonic Operands Operation (Note 1) Notes CLRVT 2080H Disable All Interupts (I Enable All Interupts (I SKIP NORML Left shift till msb shift count TRAP (SP) PC PC (2010H) PUSHA SP-2 (SP) 0000H SP SP-2 (SP)
  • Page 22 80C196KB USER’S GUIDE Table 3-2A Instruction Length (in Bytes) Opcode INDIRECT INDEXED MNEMONIC DIRECT IMMED NORMAL A-INC SHORT LONG ADD (3-op) 4 44 5 45 4 46 4 46 5 47 6 47 SUB (3-op) 4 48 5 49 4 4A 4 4A 5 4B 6 4B...
  • Page 23 80C196KB USER’S GUIDE Table 3-2B Instruction Length (in Bytes) Opcode INDIRECT INDEXED MNEMONIC DIRECT IMMED NORMAL A-INC SHORT LONG 3 A0 4 A1 3 A2 3 A2 4 A3 5 A3 3 B0 3 B1 3 B2 3 B2 4 B3 5 B3 3 C0 3 C2...
  • Page 24 80C196KB USER’S GUIDE Table 3 3A Instruction Execution State Times INDIRECT INDEXED MNEMONIC DIRECT IMMED NORMAL A-INC SHORT LONG ADD (3-op) 7 10 8 11 7 10 8 11 SUB (3-op) 7 10 8 11 7 10 8 11 ADD (2-op) SUB (2-op) ADDC SUBC...
  • Page 25 80C196KB USER’S GUIDE Table 3 3B Instruction Execution State Times MNEMONIC MNEMONIC PUSHF (int stack) PUSHF (ext stack) POPF (int stack) POPF (ext stack) PUSHA (int stack) PUSHA (ext stack) POPA (int stack) POPA (ext stack) TRAP (int stack) TRAP (ext stack) LCALL (int stack) LCALL (ext stack) SCALL (int stack)

  • Page 26: 5 80C196Kb Instruction Set Additions And Differences

    80C196KB USER’S GUIDE language and PLM-96 environment and it offers com- 3 5 80C196KB Instruction Set patibility between these environments Another advan- Additions and Differences tage is that it allows the user access to the same floating point arithmetics library that PLM-96 uses to operate For users already familiar with the 8096BH there are on REAL variables six instructions added to the standard MCS-96 instruc-...

  • Page 27: 7 Software Protection Hints

    80C196KB USER’S GUIDE When this procedure is entered at run time the stack It is recommended that unused areas of code be filled will contain the parameters in the following order with NOPs and periodic jumps to an error routine or RST (reset chip) instructions This is particularly im- portant in the code around lookup tables since if look- param1...

  • Page 28: 1 Pulse Width Modulation Output (D A)

    80C196KB USER’S GUIDE HSI TIME register When the time register is read 4 1 Pulse Width Modulation Output the next FIFO location is loaded into the holding regis- (D A) Digital to analog conversion can be done with the Pulse Three forms of HSI interrupts can be generated when a Width Modulation output The output waveform is a value moves from the FIFO into the holding register...
  • Page 29 80C196KB USER’S GUIDE HSI Trigger Options 270651– 18 270651 –19 Figure 4-3 HSI Block Diagram HIGH SPEED OUTPUT CONTROLS 6 PINS 4 SOFTWARE TIMERS 2 INTERRUPTS INITIATE A D CONVERSION RESET TIMER2 270651 –8 Figure 4-4 HSO Block Diagram...

  • Page 30: 6 A D Converter

    80C196KB USER’S GUIDE input at a time using successive approximation with a MODES OF OPERATION result equal to the ratio of the input voltage divided by Mode 0 is a synchronous mode which is commonly the analog supply voltage If the ratio is 1 00 then the used for shift register based I O expansion Sets of 8 result will be all ones A conversion can be started by bits are shifted in or out of the 80C196KB with a data...

  • Page 31: 0 Interrupts

    80C196KB USER’S GUIDE 5 0 INTERRUPTS Special Interrupts Three special interrupts available Twenty-eight (28) sources of interrupts are available on 80C196KB NMI TRAP and Unimplemented opcode the 80C196KB These sources are gathered into 15 vec- The external NMI pin generates an unmaskable inter- tors plus special vectors for NMI the TRAP instruc- rupt for implementation of critical interrupt routines tion and Unimplemented Opcodes Figure 5-1 shows...
  • Page 32 It is suggested that any unused be used in Intel development tools or evaluation boards interrupts be vectored to an error handling routine In a debug environment it may be desirable to have the rou-...

  • Page 33: 1 Interrupt Control

    80C196KB USER’S GUIDE format of these registers is the same as that of the Inter- 5 1 Interrupt Control rupt Pending Register shown in Figure 5-3 Interrupt Pending Register The INT MASK and INT MASK1 registers can be read or written as byte registers A one in any bit posi- When the hardware detects one of the sixteen inter- tion will enable the corresponding interrupt source and rupts it sets the corresponding bit in one of two pending...
  • Page 34 80C196KB USER’S GUIDE Note that location 200CH in the interrupt vector table Vector would have to be loaded with the label serial io isr Number Source Priority Location and the interrupt be enabled for this routine to execute INT15 203EH There is an interesting chain of instruction side-effects INT14 HSI FIFO Full...

  • Page 35: 3 Critical Regions

    80C196KB USER’S GUIDE Notice that the ‘‘preamble’’ and exit code for the inter- if interrupts are disabled Depending on system config- rupt service routine does not include any code for sav- urations several other SFRs might also need to be ing or restoring registers This is because it has been changed in a single instruction for the same reason assumed that the interrupt service routine has been al-...

  • Page 36: 5 Interrupt Summary

    80C196KB USER’S GUIDE POPF POP Flags pops the PSW INT MASK following EI The DI PUSHF POPF PUSHA POPA pair off the stack and TRAP instructions will also cause the same situa- tion Typically these instructions would only effect la- PUSHA PUSH All does a PUSHF then pushes tency when one interrupt routine is already in process...

  • Page 37: 0 Pulse Width Modulation Output (D A)

    80C196KB USER’S GUIDE are individually enabled by setting bits 2 and 3 of IOC1 Serial Port Interrupts bit 2 for Timer1 and bit 3 for Timer2 Which timer The serial port generates one of three possible inter- actually caused the interrupt can be determined by bits rupts Transmit interrupt TI(2030H) Receive Interrupt 4 and 5 of IOS1 bit 4 for Timer2 and 5 for Timer1 On RI(2032H) and SERIAL(200CH) Refer to section 10...
  • Page 38 80C196KB USER’S GUIDE Figure 6-2 Note that when the PWM register equals 00 the output is always low Additionally the PWM register will only be reloaded from the temporary latch when the counter overflows This means the compare circuit will not recognize a new value until the counter has expired preventing missed PWM edges The 80C196KB PWM unit has a prescaler bit (divide by 2) which is enabled by setting IOC2 2...

  • Page 39: 1 Analog Outputs

    80C196KB USER’S GUIDE drift a highly accurate 8-bit D to A converter can be 6 1 Analog Outputs made using either the HSO or the PWM output Figure 6-5 shows two typical circuits If the HSO is used the Analog outputs can be generated by two methods ei- accuracy could be theoretically extended to 16-bits ther by using the PWM output or the HSO See Section however the temperature and noise related problems...

  • Page 40: 0 Timers

    80C196KB USER’S GUIDE 7 0 TIMERS Capture Register The value in Timer2 can be captured into the T2CAP- ture register by a rising edge on P2 7 The edge must be 7 1 Timer1 held for at least one state time as discussed in the next Timer1 is a 16-bit free-running timer which is incre- section T2CAP is located at 0CH in Window 15 The mented every eight state times An interrupt can be...

  • Page 41: 4 Timer Interrupts

    80C196KB USER’S GUIDE 270651 –5 Figure 7-1 Timer Block Diagram IOC0 1 Reset Timer2 each write No action IOC0 3 Enable external reset Disable IOC0 5 HSI 0 is ext reset source T2RST is reset source IOC0 7 HSI 1 is T2 clock source T2CLK is clock source IOC1 3 Enable Timer2 overflow int...

  • Page 42: 0 High Speed Inputs

    80C196KB USER’S GUIDE Timer2 is counting up and down centered around one timer interrupts are controlled by the Interrupt Mask of the interrupt points The boundaries used to control Register bit 0 In all cases setting a bit enables a func- the Timer2 interrupt is determined by the setting of tion while clearing a bit disables it IOC2 5 When set Timer2 will interrupt on the...

  • Page 43: 1 Hsi Modes

    80C196KB USER’S GUIDE When an HSI event occurs a 7 20 FIFO stores the 16 bits of Timer1 and the 4 bits indicating which pins recorded events associated with that time tag There- fore if multiple pins are being used as HSI inputs soft- ware must check each status bits when processing on HSI event Multiple pins can recognize events with the same time tag It can take up to 8 state times for this...

  • Page 44: 3 Hsi Interrupts

    80C196KB USER’S GUIDE If the HSI TIME register is read without the holding The HSI 0 pin can generate an interrupt on the rising register being loaded the returned value will be indeter- edge even if its not enabled to the HSI FIFO An inter- minate Under the same conditions the four bits in rupt generated by this pin vectors through location HSI STATUS indicating which events have occurred...

  • Page 45: 1 Hso Interrupts And Software Timers

    80C196KB USER’S GUIDE TMR2 CHANNEL COMMAND LOCK TMR1 CLEAR CAM Lock Locks event in CAM if this is enabled by IOC2 6 (ENA LOCK) TMR TMR1 Events Based on Timer2 Based on Timer1 if 0 SET CLEAR Set HSO pin Clear HSO pin if 0 INT INT Cause interrupt No interrupt if 0 CHANNEL...

  • Page 46: 2 Hso Cam

    80C196KB USER’S GUIDE 9 2 HSO CAM SOFTWARE TIMERS The HSO can be programmed to generate interrupts at A block diagram of the HSO unit is shown in Figure 9- preset times Up to four such ‘‘Software Timers’’ can be 3 The Content Addressable Memory (CAM) file is the in operation at a time As each preprogrammed time is center of control One CAM register is compared with...

  • Page 47: 3 Hso Status

    80C196KB USER’S GUIDE 270651 –25 270651 –26 Figure 9-4 I O Status Register 0 Figure 9-5 I O Status Register 1 (IOS1) Writing the time value loads the HSO Holding Register this register in Window 15 The format for I O Status with both the time and the last written command tag Register 0 is shown in Figure 9-4 The command does not actually enter the CAM file...

  • Page 48: 5 Hso Precautions

    80C196KB USER’S GUIDE event to be cancelled by simply writing the opposite be carefully done The user should ensure writing to event to the CAM However once an entry is placed in Timer1 will not cause programmed HSO events to be the CAM it cannot be removed until either the speci- missed or occur in the wrong order The same precau- fied timer matches the written value a chip reset oc-...

  • Page 49: 7 Hso Output Timing

    80C196KB USER’S GUIDE reprogrammed in addition to the Timer2 reset com- er changes every eight state times during Phase1 From mand This method provides for up to four PWM’s an external perspective the HSO pin should change just with no software overhead except when reprogramming prior to the falling edge of CLKOUT and be stable by the duty cycle of any particular PWM The code to its rising edge Information from the HSO can be...
  • Page 50 80C196KB USER’S GUIDE pwm program ldb ioc2 0c0h flush entire cam ldb hso command 0ceh program timer2 reset time ld hso time PWM period delay eight state times before next load ldb hso command 0e6h HSO 0 1 high locked timer2 as reference ld hso time PWM period...

  • Page 51: 10 1 Serial Port Status And Control

    80C196KB USER’S GUIDE are full duplex meaning they can transmit and receive reading it accesses SP STAT The upper 3 bits of at the same time The receiver is double buffered so that SP CON must be written as 0s for future compatibil- the reception of a second byte can begin before the first ity On the 80C196KB the SP STAT register contains byte has been read The transmitter on the 80C196KB...
  • Page 52 80C196KB USER’S GUIDE The Transmitter Empty (TXE) bit is set if the transmit BAUD RATES buffer is empty and ready to take up to two characters TXE gets cleared as soon as a byte is written to SBUF Baud rates are generated based on either the T2CLK Two bytes may be written consecutively to SBUF if pin or XTAL1 pin The values used are different than TXE is set One byte may be written if TI alone is set...

  • Page 53: 10 2 Serial Port Interrupts

    80C196KB USER’S GUIDE mode the TXD pin outputs a set of 8 pulses while the 10 2 Serial Port Interrupts RXD pin either transmits or receives data Data is transferred 8 bits at a time with the LSB first A dia- The serial port generates one of three possible inter- gram of the relative timing of these signals is shown in rupts Transmit Interrupt TI(2030H) Receive Inter-...
  • Page 54 80C196KB USER’S GUIDE 270651 –29 Figure 10-3 Typical Shift Register Circuit 270651–30 270651 –31 Figure 10-4 Serial Port Frames Mode 1 2 and 3 The transmit and receive functions are controlled by port will hold off transmission until the stop bit is com- separate shift clocks The transmit shift clock starts plete RI is set when 8 data bits are received not when when the baud rate generator is initialized the receive...

  • Page 55: 10 4 Multiprocessor Communications

    80C196KB USER’S GUIDE bit is set Two types of frames are used address frames MODE 2 which have the 9th bit set and data frames which have Mode 2 is the asynchronous 9th bit recognition mode the 9th bit cleared When the master processor wants to This mode is commonly used with Mode 3 for multi- transmit a block of data to one of several slaves it first processor communications Figure 10-4 shows the data...
  • Page 56 80C196KB USER’S GUIDE The A D converter can cause an interrupt through the started The upper byte of the result register contains vector at location 2002H when it completes a conver- the most significant 8 bits of the conversion The lower sion It is also possible to use a polling method by byte format is shown in Figure 11-2 checking the Status (S) bit in the lower byte of the...

  • Page 57: 11 1 A D Conversion Process

    80C196KB USER’S GUIDE The total number of state times required for a conver- 11 1 A D Conversion Process sion is determined by the setting of IOC2 4 clock pre- scaler bit With the bit set the conversion time is 91 The conversion process is initiated by the execution of states and 158 states when the bit is cleared HSO command 0FH or by writing a one to the GO Bit...

  • Page 58: 11 3 The A D Transfer Function

    80C196KB USER’S GUIDE Placing an external capacitor on each analog input will ANGND must be connected even if the A D converter also reduce the sensitivity to noise as the capacitor is not being used Remember that Port 0 receives its combines with series resistance in the external circuit to power from the V and ANGND pins even when it...
  • Page 59 80C196KB USER’S GUIDE Figure 11-7 Ideal A D Characteristic...
  • Page 60 80C196KB USER’S GUIDE Figure 11-8 Actual and Ideal Characteristics...
  • Page 61 80C196KB USER’S GUIDE Figure 11-9 Terminal Based Characteristic...

  • Page 62: 11 4 A D Glossary Of Terms

    80C196KB USER’S GUIDE scale reference minus 1 5 LSB and it’s code widths are Undesired signals come from three main sources First all exactly one LSB These qualities result in a digitiza- noise on V Rejection Second input signal tion without offset full-scale or linearity errors In oth- changes on the channel being converted after the sam- er words a perfect conversion ple window has closed Feedthrough Third signals...
  • Page 63 80C196KB USER’S GUIDE CROSSTALK See ‘‘Off-Isolation’’ REPEATABILITY The difference between corre- sponding code transitions from different actual charac- D C INPUT LEAKAGE Leakage current to ground teristics taken from the same converter on the same from an analog input pin channel at the same temperature voltage and frequency conditions DIFFERENTIAL NON-LINEARITY The differ-...

  • Page 64: 12 0 I O Ports

    80C196KB USER’S GUIDE In addition to acting as a digital input each line of Port 12 0 I O PORTS 0 can be selected to be the input of the A D converter as discussed in Section 11 The capacitance on these There are five 8-bit I O ports on the 80C196KB Some pins is approximately 1 pF and will instantaneously in- of these ports are input only some are output only...
  • Page 65 80C196KB USER’S GUIDE 表低电平导通 270651 –40 CHMOS Configuration pFET 1 is turned on for 2 osc periods after Q makes a 0-to-1 transition During this time pFET 1 also turns on pFET 3 through the inverter to form a latch which holds the 1 pFET 2 is also on Figure 12-3 CHMOS Quasi-Bidirectional Port Circuit the low impedance pullup will remain on for one state turns on for two oscillator periods P2 remains on until...

  • Page 66: 12 3 Output Ports

    80C196KB USER’S GUIDE inputs are tied to electronic devices instead of switches the voltage present on the port pin The second case can as most external pulldowns will not hold 20 mA to 0 0 be taken care of in the software fairly easily volts IOPORT1 Writing to a Quasi-Bidirectional Port with electronic...

  • Page 67: 12 4 Ports 3 And 4 Ad0

    80C196KB USER’S GUIDE be used as inputs Reading Port 3 and 4 from a previ- 12 4 Ports 3 and 4 AD0 – 15 ously written zero condition is as follows These pins have two functions They are either bidirec- LD intregA 0FFFFH setup port...

  • Page 68: 13 0 Minimum Hardware Considerations

    80C196KB USER’S GUIDE Ports 3 and 4 on the 80C196KB are open drain ports follow good design and board layout techniques to keep There is no pullup when these pins are used as I O noise to a minimum Liberal use of decoupling caps ports A diagram of the output buffers connected to and ground planes and transient absorbers can all Ports 3 and 4 and the bus pins is shown in Figure 12-5...

  • Page 69: 13 4 Reset And Reset Status

    80C196KB USER’S GUIDE INTERNAL TIMINGS Internal operation of the chip is based on the oscillator frequency divided by two giving the basic time unit known as a ‘state time‘ With a 12 Mhz crystal a state time is 167 nS Since the 80C196KB can operate at many frequencies the times given throughout this over- view will be in state times Two non-overlapping internal phases are created by the...
  • Page 70 80C196KB USER’S GUIDE Figure 13-5 Reset Sequence...
  • Page 71 80C196KB USER’S GUIDE WATCHDOG TIMER RST INSTRUCTION There are three ways in which the 80C196KB can reset Executing a RST instruction will also reset the itself The watchdog timer will reset the 80C196KB if it 80C196KB The opcode for the RST instruction is is not cleared in 64K state times The watchdog timer is 0FFH By putting pullups on the Addr data bus unim- enabled the first time it is cleared To clear the watch-...

  • Page 72: 13 5 Minimum Hardware Connections

    80C196KB USER’S GUIDE is only asserted for four state times If this is done it is RESET CIRCUITS possible for the 80C196KB to start running before oth- The simplest way to reset an 80C196KB is to insert a er chips in the system are out of reset Software must capacitor between the RESET pin and V take this condition into account A capacitor cannot be 80C196KB has an internal pullup which has a value...

  • Page 73: 14 0 Special Modes Of Operation

    80C196KB USER’S GUIDE 270651–48 NOTE Must be driven high or low was formerly the CDE pin The CDE function is no longer available This pin must be connectd to V Figure 13-9 80C196KB Minimum Hardware Connections left floating they can float to a mid voltage level and the CPU out of the Idle Mode the CPU vectors to the draw excessive current Some pins such as NMI or corresponding interrupt service routine and begins exe-...

  • Page 74: 14 3 Once And Test Modes

    The internal current edge of RESET The only Test Mode not reserved for source that discharges the capacitor can sink approxi- use by Intel is the ONCE or ON-Circuit-Emulation mately 100 uA When the voltage goes below about 1 Mode...

  • Page 75: 15 0 External Memory Interfacing

    80C196KB USER’S GUIDE ONCE is entered by driving ALE high INST low and Address Latch Enable (ALE) provides a strobe to RD low on the rising edge of RESET All pins except transparent latches (74AC373s) to demultiplex the bus XTAL1 and XTAL2 are floated Some of the pins are To avoid confusion the latched address signals will be not truly high impedance as they have weak pullups or called MA0-MA15 and the data signals will be named...

  • Page 76: 15 2 Chip Configuration Register

    80C196KB USER’S GUIDE CLKOUT drives ALE inactive The next falling edge Mode Before the CCB fetch if the program memory is of CLKOUT asserts RD (read) and floats the bus for a external the CPU assumes that the bus is configured as read cycle During a WR (write) cycle this edge asserts an 8-bit bus In the 8-bit bus mode during the CCB WR and drives valid data on the bus On the last rising...
  • Page 77 80C196KB USER’S GUIDE This feature gives very simple and flexible ready con- hardware The ALE WR and BHE pins serve dual trol For example every slow memory chip select line functions Bits 2 and 3 of the CCR specify the function could be ORed together and connected to the READY performed by these control lines pin with Internal Ready Control programmed to insert...
  • Page 78 80C196KB USER’S GUIDE Figure 15-5 is an example of external circuitry to de- Address Valid Strobe Mode code WRL and WRH Address Valid strobe replaces ALE if CCR bit 3 is 0 When Address valid Strobe mode is selected ADV will Write Strobe Mode be asserted after an external address is setup It will stay asserted until the end of the bus cycle as shown in...

  • Page 79: 15 3 Bus Width

    80C196KB USER’S GUIDE During 16 bit bus cycles Ports 3 and 4 contain the 15 3 Bus Width address multiplexed with data using ALE to latch the address In 8-bit bus cycles Port 3 is multiplexed with The 80C196KB external bus width can be run-time address data but Port 4 only outputs the upper 8 ad- conFigured to operate as a 16 bit multiplexed address dress bits The Addresses on Port 4 are valid through-...

  • Page 80: 15 4 Hold Hlda Protocol

    80C196KB USER’S GUIDE 11001011 The external bus width can be changed every bus cycle protocol consists of three signals HOLD HLDA and if a 1 was loaded into bit CCR 1 at reset The bus width BREQ HOLD is an input asserted by a device which is changed on the fly by using the BUSWIDTH pin If requests the 80C196KB bus Figure 15-10 shows the the BUSWIDTH pin is a 1 the bus cycle is 16-bits For...
  • Page 81 80C196KB USER’S GUIDE MAXIMUM HOLD LATENCY REGAINING BUS CONTROL The time between HOLD being asserted and HLDA There is no delay from the time the 80C196KB re- being driven is known as Hold Latency After recogniz- moves HLDA to the time it takes control of the bus ing HOLD the 80C196KB waits for any current bus After HOLD is removed the 80C196KB drops HLDA cycle to finish and then asserts HLDA There are 3...

  • Page 82: 15 5 Ac Timing Explanations

    80C196KB USER’S GUIDE Case 1 Meeting Thvcl 270651 –82 Case 2 Asserting HOLD Asynchronously 270651 –83 Figure 15-12 HOLD Applied Asynchronously DISABLING HOLD REQUESTS The safest way is to add a JBC instruction to check the status of the HLDA pin after the code that clears the Clearing the HLDEN bit (WSR 7) can disable HOLD HLDEN bit Figure 15-13 is an example of code that requests when consecutive memory cycles are required...
  • Page 83 80C196KB USER’S GUIDE 270651 –80 Figure 15-14 AC Timing Diagrams...
  • Page 84 80C196KB USER’S GUIDE 270651 –81 270651 –84 Figure 15-14 AC Timing Diagrams (Continued)
  • Page 85 80C196KB USER’S GUIDE CLKOUT Low to Input Data Valid TIMINGS THE MEMORY SYSTEM MUST MEET CLDV Maximum time the memory system has ADDRESS Valid to READY Setup to output valid data after the CLKOUT AVYV Maximum time the memory system has falls to decode READY after ADDRESS is RD High to Input Data Float Time af-...
  • Page 86 80C196KB USER’S GUIDE RD Low to CLKOUT Falling Edge WR Low to WR High WR pulse width RLCL WLWH Length of time from RD asserted to Memory devices must meet this spec CLKOUT falling edge Useful for sys- Data Hold after WR Rising Edge WHQX tems based on CLKOUT Amount of time data is valid on the bus...

  • Page 87: 15 6 Memory System Examples

    80C196KB USER’S GUIDE ed in the lower half of memory and the RAM in the 15 6 Memory System Examples upper half External memory systems for the 80C196KB can be set Figure 15-18 shows a 16 bit system with 2 EPROMs up in many different ways Figure 15-16 shows a simple Again ADV is used to chip select the memory Figure 8 bit system with a single EPROM The ADV Mode...
  • Page 88 80C196KB USER’S GUIDE 270651 –69 Figure 15-19 16-Bit System with Dynamic Buswidth 270651 –70 Figure 15-20 I O Port Reconstruction...

  • Page 89: 15 7 I O Port Reconstruction

    80C196KB USER’S GUIDE The Run-Time Programming Mode allows individu- 15 7 I O Port Reconstruction al EPROM locations to be programmed at run-time under complete software control (Run-Time Pro- When a single-chip system is being designed using a gramming is done with EA 5V ) multiple chip system as a prototype it may be neces- sary to reconstruct I O Ports 3 and 4 using a memory...

  • Page 90: 16 2 Reserved Locations

    POWER-DOWN RESET 16 2 Reserved Locations All Intel Reserved locations except address 2019H when mapped internally or externally must be loaded with 0FFH to ensure compatibility with future devices Address 2019H must be loaded with 20H 270651–71...

  • Page 91: 16 3 Programming Pulse Width Register (Ppw)

    80C196KB USER’S GUIDE Mode Name Function General Programming Mode Select Determines the EPROM programming PMODE algorithm that is performed PMODE is sampled after a chip reset and (P0 –0 4 0 5 should be static while the part is operating 0 6 0 7) Auto PCCB PVER...

  • Page 92: 16 4 Auto Configuration Byte Programming Mode

    80C196KB USER’S GUIDE or WRITE lock bits are enabled some programming 16 4 Auto Configuration Byte modes will require security key verification before exe- Programming Mode cuting and some modes will not execute See Figure 16-10 and the sections on each programming mode for The Programming Chip Configuration Byte (PCCB) is details of the effects of enabling the lock bits a non-memory mapped EPROM location It gets load-...
  • Page 93 80C196KB USER’S GUIDE 270651 –72 NOTES Inputs must be driven high or low Allow RESET to rise after the voltages to V EA and V are stable Figure 16-4 Auto Programming Mode...

  • Page 94: 16 6 Slave Programming Mode

    80C196KB USER’S GUIDE The 87C196KB receives an input signal PALE to in- 16 6 Slave Programming Mode dicate a valid command is present PROG causes the 87C196KB to read in or output a data word PVER Any number of 87C196KBs can be programmed by a indicates if the programming was successful AINC au- master programmer through the Slave Programming tomatically increments the address for the Data Pro-...
  • Page 95 80C196KB USER’S GUIDE PVER is a 1 if the data program was successful PVER mand and places the value at the new address on Ports is a 0 if the data program was unsuccessful Figure 16-7 3 and 4 For example when the slave receives the com- shows the relationship of PALE PROG and PVER to mand 0100H it will place the word at internal address the Command Data path on Ports 3 and 4 for the Data...

  • Page 96: 16 7 Run-Time Programming

    80C196KB USER’S GUIDE If 16 or fewer 87C196KBs are to be gang programmed 16 7 Run-Time Programming at once a more flexible form of verification is available by giving each device a unique SID The master pro- The 87C196KB can program itself under software con- grammer can issue a Data Verify Command after the trol One byte or word can be programmed instead of Data Program Command When a verify command is...

  • Page 97: 16 8 Rom Eprom Memory Protection Options

    NOTE Substantial effort has been made to provide an excel- lent program protection scheme However Intel can- not and does not guarantee that these protection methods will always prevent unauthorized access...

  • Page 98: 16 9 Algorithms

    80C196KB USER’S GUIDE For the 87C196KB the ROM dump mode is entered Description Location Value like the other programming modes described in Section 16 1 with PMODE equal to 6H For the 83C196KB Signature Word 2070H 897CH the ROM Dump Mode is entered by placing EA at a Programming V 2072H 040H...

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