Bit Timing Equations - Intel 8XC196K Series User Manual

8XC196K x , J x , CA USER'S MANUAL
12.3.5.1

Bit Timing Equations

The bit timing equations of the integrated CAN controller are equivalent to those for the 82527
CAN peripheral with the DSC bit in the CPU interface register set (system clock divided by two).
The following equations show the timing calculations for the integrated CAN controller and the
82527 CAN peripheral, respectively.
CAN Controller CAN bus frequency
82527 CAN bus frequency
where:
F = the input clock frequency on the XTAL1 pin, in MHz
OSC
BRP = the value of the BRP bit in bit timing register 0
TSEG1 = the value of the TSEG1 field in bit timing register 0
TSEG2 = the value of the TSEG1 field in bit timing register 1
Table 12-10 defines the bit timing relationships of the CAN controller.
Timing
Parameter
t t + t
_
BITTIME SYNC SEG
t input clock period on XTAL1 (50 ns at 20 MHz operation)
1
XTAL
× (BRP + 1), where BRP is a field in bit timing register 0 (valid values are 0–63)
tq 2t
1
XTAL
t 1tq
_
SYNC SEG
(TSEG1 + 1) × tq, where TSEG1 is a field in bit timing register 1 (valid values are 2–15)
t
1
TSEG
(TSEG2 + 1) × tq, where TSEG2 is a field in bit timing register 1 (valid values are 1–7)
t
2
TSEG
(SJW + 1) × tq, where SJW is a field in bit timing register 0 (valid values are 0–3)
t
SJW
t The portion of t
PROP
the maximum sum of the physical bus delay, input comparator delay, and output driver delay,
rounded up to the nearest multiple of tq.
12-12
------------------------------------------------------------------------------------------------------------ -
=
× (
2 BRP + 1
-------------------------------------------------------------------------------------------------------------------------------------- -
=
( ) × (
DSC + 1 BRP + 1
Table 12-10. Bit Timing Relationships
+ t
1 2
TSEG TSEG
that is equivalent to PROP_SEG as defined by the CAN protocol. Twice
1
TSEG
F
osc
) × (
3 + TSEG1 + TSEG2
F
osc
) × (
3 + TSEG1 + TSEG 2
Definition
)
)