8XC196K x , J x , CA USER'S MANUAL
Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
Mnemonic
Length
POP
POPA
POPF
PUSH
PUSHA
PUSHF
Length
Mnemonic
Length
BMOV
BMOVI
LD
LDB
LDBSE
LDBZE
ST
STB
XCH
XCHB
NOTES:
1.
Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
2.
For indexed instructions, the first column lists instruction lengths as S / L , where S is the short-indexed
instruction length and L is the long-indexed instruction length.
3.
For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2's complement offset.
A-50
Stack
Direct
Immediate
Opcode
Length
2
CC
—
1
F5
—
1
F3
—
2
C8
3
1
F4
—
1
F2
—
Opcode
Length
Direct
Immediate
Opcode
Length
—
—
—
—
—
—
3
A0
4
3
B0
3
3
BC
3
3
AC
3
3
C0
—
3
C4
—
3
04
—
3
14
—
Indirect
(Note 1)
Opcode
Length
—
2
—
—
—
—
C9
2
—
—
—
—
Data
Opcode
Length
Indirect
(Note 1)
Opcode
Length
—
3
—
3
A1
3
B1
3
BD
3
AD
3
—
3
—
3
—
—
—
—
Indexed
(Notes 1, 2)
Length
Opcode
Opcode
S/L
CE
3/4
CF
—
—
—
—
—
—
CA
3/4
CB
—
—
—
—
—
—
Opcode
Length
Opcode
Indexed
(Notes 1, 2)
Length
Opcode
Opcode
S/L
C1
—
—
CD
—
—
A2
4/5
A3
B2
4/5
B3
BE
4/5
BF
AE
4/5
AF
C2
4/5
C3
C6
4/5
C7
—
4/5
0B
—
4/5
1B