Intel 8XC196K Series User Manual page 290

Table of Contents

Figure 12-5. A Bit Time as Implemented in the CAN Controller

Table 12-9. CAN Controller Bit Time Segments

This time segment is equivalent to SYNC_SEG in the CAN protocol. Its length is one time

This time segment is equivalent to the sum of PROP_SEG and PHASE_SEG1 in the CAN

protocol. Its length is specified by the TSEG1 field in bit timing register 1. To allow for resyn-

chronization, the sample point can be moved (t

lengthened) by 1 to 4 time quanta, depending on the programmed value of the SJW field in bit

timing register 0.

The CAN controller samples the bus once or three times, depending on the value of the

sampling mode (SPL) bit in bit timing register 0. In three-sample mode, the hardware

case, the "sample point" shown in Figure 12-5 is the time of the third sample; the first and

second samples occur 2 and 1 time quanta earlier, respectively.

This time segment is equivalent to PHASE_SEG2 in the CAN protocol. Its length is specified

by the TSEG2 field in bit timing register 1. To allow for resynchronization, the sample point

can be moved (t

quanta, depending on the programmed value of the SJW field in bit timing register 0.

CAN SERIAL COMMUNICATIONS CONTROLLER

(TSEG1 + 1)tq

by 2 time quanta to allow time for the additional two bus samples. In this

can be shortened and the other lengthened) by 1 to 4 time

(TSEG2 + 1)tq

can be shortened and the other