Intel Agilex Configuration User Manual
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Intel Agilex Configuration User Manual

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Configuration User Guide
UG-20205 | 2019.10.09
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  • Page 1 ® ™ Intel Agilex Configuration User Guide ® ® Updated for Intel Quartus Prime Design Suite: 19.3 Subscribe UG-20205 | 2019.10.09 Send Feedback Latest document on the web: HTML...

  • Page 2: Table Of Contents

    3.1.7. QSF Assignments for Avalon-ST x8........................53 3.1.8. QSF Assignments for Avalon-ST x16........................55 3.1.9. QSF Assignments for Avalon-ST x32........................57 3.1.10. IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core......59 Intel ®...
  • Page 3 3.2.7. Serial Flash Memory Layout..........................99 3.2.8. AS_CLK............................... 100 3.2.9. Active Serial Configuration Software Settings ....................101 3.2.10. Intel Quartus Prime Programming Steps......................102 3.2.11. Debugging Guidelines for the AS Configuration Scheme..................106 3.2.12. QSF Assignments for AS..........................108 3.3. SD/MMC Configuration..............................111 3.3.1.
  • Page 4 6.7.1. nCONFIG..............................188 6.7.2. nSTATUS..............................188 6.7.3. CONF_DONE and INIT_DONE..........................189 6.7.4. SDM_IO Pins..............................190 7. Intel Agilex Configuration User Guide Archives........................193 8. Document Revision History for the Intel Agilex Configuration User Guide................194 Intel ® Agilex ™ Configuration User Guide...

  • Page 5: Intel ® Agilex ™ Configuration User Guide

    Secure Digital and Multi Media Card (SD/MMC) Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
  • Page 6 You can configure the Intel Agilex device using the dedicated JTAG pins. The JTAG port provides seamless access to many useful tools and functions. In addition to configuring the Intel Agilex, you use the JTAG port for debugging with Signal Tap or the System Console tools.
  • Page 7 MSEL CvP uses an external PCIe* host device as a Root Port to configure the Intel Agilex device over the PCIe link. You can specify up to a x16 PCIe link. Typically, the bitstream compression ratio and the SDM input buffer data rate, not the PCIe link, limit the configuration data rate Intel Agilex devices support two CvP modes, CvP init and CvP update.

  • Page 8: Configuration And Related Signals

    Intel Agilex device accesses flash memory immediately after exiting reset. The power supply must be able to provide an equally fast ramp up for the Intel Agilex device and the external AS x4 flash devices. Failing to meet this requirement causes the SDM to report that the memory is missing.

  • Page 9: Intel Download Cables Supporting Configuration In Intel Agilex Devices

    1.1.2. Intel Download Cables Supporting Configuration in Intel Agilex Devices Intel provides the following cables to download your design to the Intel Agilex device on the PCB. Download cables support prototyping activity by providing detailed debug messages via Intel Quartus Prime Programmer. You must use Intel download cables for advanced debugging using the Signal Tap logic analyzer or the System Console tools.
  • Page 10 1. Intel Agilex Configuration User Guide UG-20205 | 2019.10.09 Intel FPGAs and Programmable Devices / Download Cables provides more information about the download cables and includes links to the user guides for all cables listed in the table above. Intel ®...

  • Page 11: Intel Agilex Configuration Architecture

    The Secure Device Manager (SDM) is a triple-redundant processor-based module that manages configuration and the security features of Intel Agilex devices. The SDM is available on all Intel Agilex FPGAs and SoC devices. The block diagram below provides an overview of the Intel Agilex configuration architecture which includes the following blocks: •...

  • Page 12: Secure Device Manager

    Configuration bitstream authentication: After power-on during startup, the SDM triple-redundant lockstep processors run code from the boot ROM. The boot ROM code authenticates the Intel-generated configuration firmware and configuration bitstream, ensuring that configuration bitstream is from a trusted source. All Intel Agilex support authentication.
  • Page 13 ® ™ 1. Intel Agilex Configuration User Guide UG-20205 | 2019.10.09 Figure 3. SDM Block Diagram FPGA Core Secure Device Manager CRAM Communication Lockstep Processors Sensors Boot ROM Temperature SEU Detection Voltage Chip ID Serial Flash Peripherals Crypto IP Mailbox Client IP...
  • Page 14 When you generate a configuration bitstream using the File Programming File Generator menu item, the bitstream assembler adds all firmware (including the SDM firmware) that matches the Intel Quartus Prime Pro Edition Release to .sof Depending on the configuration scheme you specify the resulting file can be in any of the following formats: •...
  • Page 15 1.2.1.2. Specifying Boot Order for Intel Agilex SoC Devices For Intel Agilex SoC devices you can specify the configuration order, choosing either the FPGA First or the Hard Processor System (HPS) First options. When you select the FPGA First option, the SDM fully configures the FPGA, then configures the HPS SDRAM pins, loads the HPS first stage boot loader (FSBL) and takes the HPS out of reset.

  • Page 16: Intel Agilex Configuration Details

    Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
  • Page 17 HPS such as U-Boot or the operating system (OS) initiates the configuration, the FPGA configures and enters user mode.. The entire device does not enter user mode simultaneously. Intel requires you to include the Reset Release Intel FPGA IP on page 23 in your design.
  • Page 18 Power Supply Status The power-on reset (POR) holds the Intel Agilex device in the reset state until the power supply outputs are within the recommended operating range. defines the maximum power supply ramp time. If POR does not meet the...
  • Page 19 For the following timing diagrams that define set-up, hold, and propagation delay timing parameters: AS Configuration Serial Output Timing Diagram, AS Configuration Serial Input Timing Diagram, and Avalon ST Configuration Timing Diagram. • Intel Agilex Power Management User Guide Intel ® Agilex ™...

  • Page 20: Configuration Flow Diagram

    2. Intel Agilex Configuration Details UG-20205 | 2019.10.09 2.2. Configuration Flow Diagram This topic describes the configuration flow for Intel Agilex devices. Figure 5. Intel Agilex FPGA Configuration Flow Configuration Pass Flow nSTATUS = HIGH Configuration Fail Flow Device Reconfiguration Flow...
  • Page 21 UG-20205 | 2019.10.09 Power Up • The Intel Agilex power supplies power following the guidelines in the Power-Up Sequence Requirements for Intel Agilex Devices section of the Intel Agilex Power Management User Guide. • A device-wide power-on reset (POR) asserts after the power supplies reach the correct operating voltages. The external power supply ramp must not be slower than the minimum ramping rate until the supplies reach the operating voltage.
  • Page 22 JTAG Configuration Note: You can perform JTAG configuration anytime from any state except the power-on and SDM startup state. The Intel Agilex device cancels the previous configuration and accepts the reconfiguration data from the JTAG interface. The signal nCONFIG must be held in a stable state during JTAG configuration.

  • Page 23: Reset Release Intel Fpga Ip

    INIT_DONE hold your design in reset until configuration is complete. The Reset Release Intel FPGA IP is available in the Intel Quartus Prime Software. This IP consists of a single output signal, . The signal is the core version of the...
  • Page 24 UG-20205 | 2019.10.09 Figure 7. Reset Release Intel FPGA IP INIT_DONE External Connection If you do not include the Reset Release Intel FPGA IP in your design, you must feed the signal back into your INIT_DONE design as an input to your reset logic as shown in this figure.

  • Page 25: Additional Clock Requirements For Hps, Pcie, And Hbm2

    The Intel Agilex device has additional clock requirements for PCIe, HPS EMIF IP, eSRAM, and the High Bandwidth Memory (HBM2) IP. To avoid configuration failures, the Intel Agilex device requires additional clocks for transceivers, PCIe, HPS EMIF IP, and all E- tile variants. You must provide a free-running, stable reference clock to these blocks before configuration begins. This...

  • Page 26: Sdm Pin Mapping

    SDM I/O pin functions using the Device Configuration Device and Pin Options dialog box in the Intel Quartus Prime software. All SDM input signals include Schmitt triggers. All SDM outputs are open collector. Fixed SDM I/O Pin Assignments for Avalon-ST x8 and AS x4 The Avalon-ST x8 and AS x4 configuration schemes use the dedicated SDM I/O pin assignments listed in in the table below.

  • Page 27: Msel Settings

    If you use AS Fast mode and are not concerned about 100 ms PCIe linkup, you must still ramp the supply within 18 ms. CCIO_SDM This ramp-up requirement ensures that the AS x4 device is within its operating voltage range when the Intel Agilex device begins to access it. Intel ®...

  • Page 28: Device Configuration Pins For Optional Configuration Signals

    2.5.3. Device Configuration Pins for Optional Configuration Signals All configuration schemes use the same dedicated pins for the standard control signals shown in the Intel Agilex Configuration Timing Diagram. Many other optional configuration signals do not have dedicated pin assignments.
  • Page 29 2. Intel Agilex Configuration Details UG-20205 | 2019.10.09 Table 5. Available SDM I/O Pin Assignments for Configuration Signals that Do Not Use Dedicated SDM I/O Pins Configuration Scheme Signal Names Avalon-ST AS x4 PWRMGT_SCL SDM_IO0 SDM_IO0 SDM_IO0 SDM_IO0 SDM_IO14 SDM_IO14...
  • Page 30 2. Intel Agilex Configuration Details UG-20205 | 2019.10.09 Configuration Scheme Signal Names Avalon-ST AS x4 SDM_IO5 SDM_IO5 SDM_IO14 SDM_IO6 SDM_IO6 SDM_IO15 SDM_IO7 SDM_IO7 SDM_IO16 SDM_IO9 SDM_IO9 SDM_IO10 SDM_IO10 SDM_IO11 SDM_IO11 SDM_IO12 SDM_IO12 SDM_IO13 SDM_IO13 SDM_IO14 SDM_IO14 SDM_IO15 SDM_IO15 SDM_IO16 SDM_IO16...
  • Page 31 2. Intel Agilex Configuration Details UG-20205 | 2019.10.09 Configuration Scheme Signal Names Avalon-ST AS x4 SDM_IO13 SDM_IO13 SDM_IO14 SDM_IO14 SDM_IO15 SDM_IO15 SDM_IO16 SDM_IO16 HPS_COLD_nRESET SDM_IO0 SDM_IO0 SDM_IO0 SDM_IO0 SDM_IO5 SDM_IO1 SDM_IO1 SDM_IO10 SDM_IO7 SDM_IO2 SDM_IO2 SDM_IO11 SDM_IO9 SDM_IO3 SDM_IO3 SDM_IO12...
  • Page 32 2. Intel Agilex Configuration Details UG-20205 | 2019.10.09 Configuration Scheme Signal Names Avalon-ST AS x4 SDM_IO7 SDM_IO2 SDM_IO2 SDM_IO11 SDM_IO9 SDM_IO3 SDM_IO3 SDM_IO12 SDM_IO12 SDM_IO4 SDM_IO4 SDM_IO13 SDM_IO16 SDM_IO5 SDM_IO5 SDM_IO14 SDM_IO6 SDM_IO6 SDM_IO15 SDM_IO7 SDM_IO7 SDM_IO16 SDM_IO9 SDM_IO9 SDM_IO10...
  • Page 33 SDM I/O pins 0 or 16. These pins have weak CONF_DONE INIT_DONE internal pull-downs resistors. If you cannot use these pins, Intel recommends that you include external 4.7-kΩ pull-down resistors to avoid false signaling. 2.5.3.1. Specifying Optional Configuration Pins You enable and assign the SDM I/O pins using the Intel Quartus Prime software.
  • Page 34 2. Intel Agilex Configuration Details UG-20205 | 2019.10.09 4. Click OK to confirm and close the Configuration Pin dialog box. Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 35 2. Intel Agilex Configuration Details UG-20205 | 2019.10.09 2.5.3.2. Enabling Dual-Purpose Pins , and are dual-purpose pins. Once the AVST_CLK AVST_DATA[15:0] AVST_DATA[31:16] AVST_READY AVST_VALID device enters user mode these pins can function either as GPIOs or as tri-state inputs. If you use these pins as GPIOs, make the following assignments: •...
  • Page 36 AVST_DATA GPIO bank You can download the IBIS models from the IBIS Models for Intel Devices web page. The Intel Quartus Prime software does not support IBIS model generation for configuration pins in the current release. Slow slew rate signal Intel ®...
  • Page 37 Specifying the Slave Device Type for Power Management and VID Recommended Setting Other (Not Recommended) Refer to the Intel Agilex Power Management User Guide for more information about the pin assignments and PMBus setting. Related Information Intel Agilex Power Management User Guide 2.5.3.5.

  • Page 38: Configuration Clocks

    PR_READY • PR_ERROR • PR_DONE Connect these partial reconfiguration signals to the Partial Reconfiguration External Configuration Controller Intel FPGA IP. Related Information Creating a Partial Reconfiguration Design 2.6. Configuration Clocks 2.6.1. Setting Configuration Clock Source You must specify the configuration clock source by selecting either the internal oscillator or...

  • Page 39: Osc_Clk_1 Clock Input

    Intel Quartus Prime OSC_CLK_1 OSC_CLK_1 software, the device loads the majority of the configuration bitstream at 250 MHz. Intel Agilex devices include an internal oscillator in addition to which runs the configuration process at a frequency between 170-230 MHz. Intel Agilex OSC_CLK_1 devices always use this internal oscillator to load the first section of the bitstream, approximately 200 kilobyte (KB).
  • Page 40 OSC_CLK_1 source enables the fastest possible configuration. Refer to Setting Configuration Clock Source for instructions OSC_CLK_1 setting this frequency using the Intel Quartus Prime Software. You can also specify this frequency by editing your file. Here are the possible assignments: .qsf...

  • Page 41: Intel Agilex Configuration Schemes

    FPGA. The logic that controls the configuration process resides in the external host. You can use the PFL II IP with a MAX II, MAX V, or Intel MAX 10 device as the host to read configuration data from the flash memory device and configure the Intel Agilex device.
  • Page 42 Avalon Interface Specifications for protocol details. Related Information • Avalon Interface Specifications • Intel Agilex Device Data Sheet is required if you are using the Intel FPGA Parallel Flash Loader II IP as the configuration host. CONF_DONE Intel ® Agilex ™...

  • Page 43: Avalon-St Configuration Scheme Hardware Components And File Types

    A custom host, typically a microprocessor, with any external memory • The Intel FPGA Download Cable II to connect the Intel Quartus Prime Programmer to the PCB. The following block diagram illustrates the components and design flow using the Avalon-ST configuration scheme.

  • Page 44: Enabling Avalon-St Device Configuration

    Note: Intel Agilex devices using Avalon ST x32 configuration and DDR x72 external memory interfaces are limited to a maximum of three memory interfaces. The Avalon ST x8 and x16 can support up to four DDR x72 external memory interfaces.

  • Page 45: The Avst_Ready Signal

    The configuration files for Intel Agilex devices can be highly compressed. During configuration, the decompression of the bit stream inside the device requires the host to pause before sending more data. The Intel Agilex device asserts the signal when the device is ready to accept data. The...
  • Page 46 If you use the PFL II IP core as the configuration host, you can use the Intel Quartus Prime software to store the binary configuration data to the flash memory through the PFL II IP core.
  • Page 47 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Avalon-ST x8 configuration scheme uses the SDM pins only. Avalon-ST x16 and x32 configuration scheme only use dual- purpose I/O pins that you can use as general-purpose I/O pins after configuration. Related Information...

  • Page 48: Rbf Configuration File Format

    3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 3.1.4. RBF Configuration File Format If you do not use the Parallel Flash Loader II Intel FPGA IP core to program the flash, you must generate the file. .rbf The data in file are in little-endian format .rbf...

  • Page 49: Avalon-St Single-Device Configuration

    3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 3.1.5. Avalon-ST Single-Device Configuration Figure 13. Connections for Avalon-ST x8 Single-Device Configuration CCIO_SDM Configuration CCIO_SDM Control Signals External Host 10kΩ 10kΩ Intel FPGA CPLD / FPGA fpga_nconfig nCONFIG fpga_nstatus nSTATUS fpga_conf_done CONF_DONE...
  • Page 50 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 14. Connections for Avalon-ST x16 Single-Device Configuration CCIO_SDM CCIO_SDM 10kΩ External Host Configuration 10kΩ Control Signals Intel FPGA CPLD / FPGA fpga_nconfig nCONFIG fpga_nstatus nSTATUS fpga_conf_done CONF_DONE INIT_DONE Parallel Flash Loader II IP...
  • Page 51 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 15. Connections for Avalon-ST x32 Single-Device Configuration CCIO_SDM CCIO_SDM Configuration External Host 10kΩ Control Signals 10kΩ Intel FPGA CPLD / FPGA nCONFIG fpga_nconfig nSTATUS fpga_nstatus CONF_DONE fpga_conf_done INIT_DONE Parallel Flash Loader II IP...

  • Page 52: Debugging Guidelines For The Avalon-St Configuration Scheme

    3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Notes for Figure: 1. Refer to MSEL Settings for the correct resistor pull-up and pull-down values for all configuration schemes. 2. The pins are dual-purpose. After power-on, you can reassign these pins to other functions. For more information,...

  • Page 53: Qsf Assignments For Avalon-St X8

    Avalon-ST x8 configuration. These settings are for a Intel Agilex SmartVID device operating in PMBus slave mode which requires most of the SDM_IO pins. Refer to the Intel Agilex Power Management User Guide for the PMBus constraints in master mode.
  • Page 54 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 16. Set SDM_IO Configuration Pins Using the Intel Quartus Prime Software Related Information • PMBus Master Mode ® In the Intel Stratix 10 Power Management User Guide • Intel Quartus Prime Pro Settings File Reference Manual Intel ®...

  • Page 55: Qsf Assignments For Avalon-St X16

    Avalon-ST x16 configuration. These settings are for a Intel Agilex SmartVID device operating in PMBus slave mode which requires most of the SDM_IO pins. Refer to the Intel Agilex Power Management User Guide for the PMBus constraints in master mode.
  • Page 56 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 17. Set SDM_IO Configuration Pins Using the Intel Quartus Prime Software Related Information • PMBus Master Mode ® In the Intel Stratix 10 Power Management User Guide • Intel Quartus Prime Pro Settings File Reference Manual Intel ®...

  • Page 57: Qsf Assignments For Avalon-St X32

    Avalon-ST x32 configuration. These settings are for a Intel Agilex SmartVID device operating in PMBus slave mode which requires most of the SDM_IO pins. Refer to the Intel Agilex Power Management User Guide for the PMBus constraints in master mode.
  • Page 58 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 18. Set SDM_IO Configuration Pins Using the Intel Quartus Prime Software Related Information • PMBus Master Mode ® In the Intel Stratix 10 Power Management User Guide • Intel Quartus Prime Pro Settings File Reference Manual Intel ®...

  • Page 59: Ip For Use With The Avalon-St Configuration Scheme: Intel Fpga Parallel Flash Loader Ii Ip Core

    3.1.10. IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core 3.1.10.1. Functional Description You can use the Parallel Flash Loader II Intel FPGA IP (PFL II) with an external host, such as the MAX II, MAX V, or Intel MAX 10 devices to complete the following tasks: •...
  • Page 60 3.1.10.1.2. Controlling Avalon-ST Configuration with PFL II IP Core The PFL II IP core in the host determines when to start the configuration process, read the data from the flash memory device, and configure the Intel Agilex device using the Avalon-ST configuration scheme. Intel ®...
  • Page 61 You have JTAG or In-System Programming (ISP) access to the configuration host. • You want to program the flash memory device with non-Intel FPGA data, for example initialization storage for an ASSP. You can use the PFL II IP core to program the flash memory device for the following purposes: —...
  • Page 62 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 22. Flash Memory in 8-Bit Mode The address connection between the PFL II IP core and the flash memory device are the same. address: 24 bits address: 24 bits PFL II Flash Memory Figure 23.
  • Page 63 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 24. Cypress and Micron M28, M29 Flash Memory in 8-Bit Mode The flash memory addresses in Cypress 8-bit flash shifts one bit up. Address bit 0 of the PFL II IP core connects to data pin of the flash memory.
  • Page 64 0×2000 • Auto mode—allows the Intel Quartus Prime software to automatically determine the start address of the page. The Intel Quartus Prime software aligns the pages on a 128 KB boundary. If the first valid start address is , the next valid...
  • Page 65 UG-20205 | 2019.10.09 You set the option bits in the PFL II IP Intel FPGA IP using the parameter editor. By default the PFL II IP displays Flash Programming for the What operating mode will be used? parameter. In this default state, the FPGA Configuration tab is not visible.
  • Page 66 EDIT to specify the Start address for the option bits. This Start address must match the address you specify for What is the byte address of the option bits, in hex? when specifying the PFL II IP parameters. The Intel Quartus Prime Programming File Generator generates the information for the version when you convert .pof...
  • Page 67 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Table 12. Option Bits Sector Format Sector Offset Value – Page 0 start address 0x00 0x03 – Page 0 end address 0x04 0x07 Page 1 start address – 0x08 0x0B Page 1 end address –...
  • Page 68 32-bit value of the sector offset address. If you encounter a configuration error you can verify that the generated bitstream addresses match the addresses you specified in the Intel Quartus Prime Software. The following table shows the bit fields of the start address.
  • Page 69 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Sector Offset Value – 0x0C 0x0F 0x00352E30 For Page 0 if you append the start address bits[31:11] with , the result is 13'b0000000000000 32'b00000000000000010000000000000000 = 0x10000 If you append the end address...
  • Page 70 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 28. Implementing Page Mode and Option Bits in the CFI Flash Memory Device 8 Bits End Address Option Bits Configuration Data (Page 2) 32 Bits Configuration Data (Page 1) Page 2 Address + Page-Valid...
  • Page 71 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 29. Page Start Address, End Address, and Page-Valid Bit Stored as Option Bits The Page-Valid bits indicate whether each page is successfully programmed. The PFL II IP core sets the Page-Valid bits after successfully programming the pages.
  • Page 72 1. Click File Programming File Generator. 2. For Device family select Intel Agilex. 3. For Configuration mode select Avalon-ST configuration scheme that you plan to use. 4. For Output directory, click Browse to select your output file directory.
  • Page 73 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 30. Programming File Generator Output Files Tab Select Device and Configuration Mode Select Output Files To Generate, Input File Source, and Configuration Device Generate Selected Files 8. To specify a that contains the configuration bitstream, on the Input Files tab, click Add Bitstream.
  • Page 74 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Input Files 9. To include raw data, click Add Raw Data and specify a Hexadecimal (Intel-Format) Output File ( ) or binary ( .hex .bin file. This step is optional. 10. On the Configuration Device tab, click Add device. The Add Device dialog box appears. Select your flash device from the drop-down list of available parallel flash devices.
  • Page 75 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 31. Edit Partition: OPTIONS for Flash Device Start address 12. With the flash device selected, click Add Partition to specify a partition in flash memory. Intel ® Agilex ™ Configuration User Guide...
  • Page 76 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 32. Add Flash Device and Partition Configuration Device a. For Name select a Partition name. b. For Input File specify the .sof From the Page dropdown list, select the page to write this .sof...
  • Page 77 PFL II block to tri-state the correct FPGA configuration pins. 3.1.10.2.3. Programming CPLDs and Flash Memory Devices Sequentially This procedure provides a single set of instructions for the Intel Quartus Prime Programmer to configure the CPLD and write the flash memory device.
  • Page 78 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 1. Open the Programmer and click Add File to add the for the CPLD. .pof 2. Right-click the CPLD .pof and click Attach Flash Device. 3. In the Flash Device menu, select the appropriate density for the flash memory device.
  • Page 79 Add a new Intel- or AMD-compatible CFI flash memory device into the PFL II-supported flash database. Edit Edit the parameters of the newly added Intel- or AMD-compatible CFI flash memory device in the PFL II-supported flash database. Remove Remove the newly added Intel- or AMD-compatible CFI flash memory device from the PFL II-supported flash database.
  • Page 80 Specify the CFI flash extended device identifier, only applicable for AMD-compatible CFI flash memory device Flash device is Intel compatible Turn on the option if the CFI flash is Intel compatible Typical word programming time Typical word programming time value in µs unit Maximum word programming time Maximum word programming time value in µs unit...
  • Page 81 5. After you add, update, or remove the new CFI flash memory device, click OK. The Windows registry stores user flash information. Consequently, you must have system administrator privileges to store the parameters in the Define New CFI Flash Device window in the Intel Quartus Prime Pro Edition Programmer. 3.1.10.3. PFL II Parameters Table 18.
  • Page 82 Specifies the flash access time. This information is available from the flash datasheet. access time? Intel recommends specifying a flash access time that is equal to or greater than the required time. For CFI parallel flash, the unit is in ns. For NAND flash, the unit is in μs. NAND flash uses pages instead of bytes and requires greater access time.
  • Page 83 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Options Value Description What is the byte Provide the byte address of the option bits. Specifies the option bits start address in flash memory. The start address must reside on address of the option an 8 KB boundary.
  • Page 84 Intel Burst mode • Normal mode—applicable for all flash memory • 16 byte page mode (GL only) • Intel Burst mode—Applicable for devices that support bursting. Reduces sequential • 32 byte page mode (MT23EW) read access time • Micron Burst Mode (M58BW) •...
  • Page 85 The width of this port depends on the number of flash memory devices in the chain. continued... Intel recommends that you do not insert logic between the PFL II pins and the host I/O pins, especially on the flash_data pins.

  • Page 86: As Configuration

    3.2. AS Configuration In AS configuration schemes, the SDM block in the Intel Agilex device controls the configuration process and interfaces. The serial flash configuration device stores the configuration data. During AS Configuration, the SDM first powers on with the boot ROM.
  • Page 87 Required Configuration Signals for the AS Configuration Scheme You specify SDM I/O pin functions using the Device Configuration Device and Pin Options dialog box in the Intel Quartus Prime software. You can reassign the GPIO, dual-purpose configuration pins for other functions in user mode. Configuration Function...

  • Page 88: As Configuration Scheme Hardware Components And File Types

    • Quad SPI flash memory • The Intel FPGA Download Cable II to connect the Intel Quartus Prime Programmer to the PCB. The following block diagram illustrates the components and design flow using the AS configuration scheme. Figure 34. Components and Design Flow for .jic Programming...
  • Page 89 SDM firmware programming. The helper SOF image provides the required SDM firmware. You initially use the JTAG cable to load a SDM Helper SOF into the Intel Agilex device. The SDM can then load the flash device with the Intel Agilex design.

  • Page 90: As Single-Device Configuration

    3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 3.2.2. AS Single-Device Configuration Figure 35. Connections for AS x4 Single-Device Configuration CCIO_SDM Configuration 10kΩ Control Signals 10kΩ Intel FPGA nCONFIG nSTATUS Optional CONF_DONE Monitoring INIT_DONE Optional OSC_CLK_1 MSEL MSEL[2:0] CCIO_SDM Pin 1...

  • Page 91: As Using Multiple Serial Flash Devices

    UG-20205 | 2019.10.09 3.2.3. AS Using Multiple Serial Flash Devices Intel Agilex devices support one AS x4 flash memory device for AS configuration and up to three AS x4 flash memories for use with HPS data storage. The pins are dual-purpose and operate as only during POR state.
  • Page 92 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 36. Connections for AS Configuration with Multiple Serial Flash Devices CCIO_SDM Configuration 10kΩ Control Signals 10kΩ Intel FPGA nCONFIG nSTATUS Optional CONF_DONE Monitoring INIT_DONE Optional OSC_CLK_1 MSEL MSEL[2:0] CCIO_SDM Configuration Pin 1...

  • Page 93: As Configuration Timing Parameters

    3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 The following table shows the maximum supported frequency for a range of capacitance loading values when using AS_CLK multiple flash devices. The maximum frequency also depends on whether you use the or internal...

  • Page 94: Maximum Allowable External As_Data Pin Skew Delay Guidelines

    The capacitance loading of the flash device The table below lists the maximum allowable skew delay depending on the AS_CLK frequency. Intel recommends that you to perform IBIS simulations to ensure that the skew delay does not exceed the maximum delay specified in this table.

  • Page 95: Programming Serial Flash Devices

    . The Intel Quartus Prime Programmer programs the flash memory devices via the AS AS_DATA3 AS_nCS0 AS_nCS3 header. If you are using the Generic Serial Flash Interface Intel FPGA IP to write the flash memory the flash device must be connected to GPIO to access the flash device. Intel ®...
  • Page 96 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 39. AS Programming Using Intel Quartus Prime or Third-Party Programmer CCIO_SDM 10 kΩ 10 kΩ Intel FPGA AS x4 Flash External clock source nSTATUS to is optional. nCONFIG CONF_DONE DATA0 AS_DATA[0]...
  • Page 97 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 3.2.6.2. Programming Serial Flash Devices using the JTAG Interface The Intel Quartus Prime Programmer interfaces to the SDM device through JTAG interface and programs the serial flash device. The SDM emulates AS programming. Figure 40.
  • Page 98 AS fast mode: Pull MSEL [1] low using 4.7 kΩ resistor AS normal mode: Pull MSEL [1] high using 4.7 kΩ resistor Intel recommends using the JTAG interface to prepare the Quad SPI flash device for later use in AS mode. Intel ® Agilex ™...

  • Page 99: Serial Flash Memory Layout

    3. The programmer first configures the SDM with configuration firmware. Then, the SDM drives configuration data from the programmer to the AS x4 flash device using SDM_IOs. 4. To use the Intel Agilex device in AS mode after successful programming of the flash device, set the pins to either AS MSEL fast or AS normal mode and power cycle the device.

  • Page 100: As_Clk

    Once loaded, if the flash size is 256 Mb or larger, the SDM configures the Quad SPI flash to operate in 4-byte addressing mode and continues to load the rest of the bitstream until configuration completes. Intel Agilex devices support the following third-party flash devices operating at 1.8 V: •...

  • Page 101: Active Serial Configuration Software Settings

    71.5 3.2.9. Active Serial Configuration Software Settings You must set the parameters in the Device and Pin Options of the Intel Quartus Prime software when using the AS configuration scheme. To set the parameters for AS configuration scheme, complete the following steps: 1.

  • Page 102: Intel Quartus Prime Programming Steps

    Generating an Application .rpd Image on page 153 in the Remote System Update chapter. This procedure generates flash programming files for Intel Agilex devices. Complete the following steps generate the programming file or files you require: 1. Click File Programming File Generator.
  • Page 103 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 43. Programming File Generator Output Files Device Family Configuration Mode Output Directory Name Output Files Required 6. For the JTAG Indirect Configuration File (.jic) and Programmer Object File (.pof) you can turn on the Memory Map File (.map).
  • Page 104 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 44. Programming File Generator Input Files Input Files 8. On the Configuration Device tab, click Add Device. You can select your flash device from the from the Configuration Device list, or define a custom device using the available menu options. For more information about defining a custom...
  • Page 105 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 45. Programming File Generator Input Files Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 106: Debugging Guidelines For The As Configuration Scheme

    .poc .jic configuration device. The Intel Quartus Prime Programmer uses this additional data to establish communication with the configuration device and then write the programming data. 9. Click Generate to generate the programming file or files.
  • Page 107 AS_nCS0 AS_nCS3 to JTAG. If is either AS fast or normal, the SDM drives the AS pins until you power cycle the Intel Agilex device. MSEL MSEL Unlike earlier device families, the AS pins are not tristated when the device enters user mode.

  • Page 108: Qsf Assignments For As

    AS configuration. These settings are for a Intel Agilex SmartVID device operating in PMBus slave mode which requires most of the SDM_IO pins. Refer to the Intel Agilex Power Management User Guide for the PMBus constraints in master mode.
  • Page 109 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 # Configuration settings # ====================== set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4" set_global_assignment -name USE_CONFIGURATION_DEVICE ON set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 set_global_assignment -name GENERATE_PR_RBF_FILE ON set_global_assignment -name ENABLE_ED_CRC_CHECK ON set_global_assignment -name MINIMUM_SEU_INTERVAL 479 # SmartVID feature PMBus settings [Slave mode settings only] # ========================================================== set_global_assignment -name VID_OPERATION_MODE "PMBUS SLAVE"...
  • Page 110 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 Figure 46. Set SDM_IO Configuration Pins Using the Intel Quartus Prime Software Related Information • PMBus Master Mode In the Power Management User Guide • Intel Quartus Prime Pro Settings File Reference Manual Intel ®...

  • Page 111: Sd/Mmc Configuration

    3'b100 Table 30. Required Configuration Signals for the SD/MMC Configuration Scheme You specify SDM I/O pin functions using the Device Configuration Device and Pin Options dialog box in the Intel Quartus Prime software. Configuration Function Direction Powered by SDM I/O...

  • Page 112: Sd/Mmc Single-Device Configuration

    3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 3.3.1. SD/MMC Single-Device Configuration Figure 47. Connections for SD/MMC Single-Device Configuration CCIO_SDM Configuration 10kΩ Control Signals 10kΩ Intel FPGA nCONFIG nSTATUS Optional CONF_DONE Monitoring INIT_DONE Optional OSC_CLK_1 MSEL MSEL[2:0] Configuration Control Signals...

  • Page 113: Jtag Configuration

    .sof .sof JTAG programmer to configure the Intel Agilex device. The Intel FPGA Download Cable II and the Intel FPGA Ethernet Cable both can support the V supply at 1.8 V. Alternatively, you can use the JamSTAPL Format File ( ) or Jam Byte Code .jam...

  • Page 114: Jtag Configuration Scheme Hardware Components And File Types

    INIT_DONE Note: Pin-Out files are not yet available for Intel Agilex devices.Intel Agilex Related Information Programming Support for Jam STAPL Language 3.4.1. JTAG Configuration Scheme Hardware Components and File Types The following figure illustrates JTAG programming.

  • Page 115: Jtag Device Configuration

    The configuration data is available on the pin one clock cycle later. You can configure the Intel Agilex device through JTAG using a download cable or a microprocessor. Intel ® Agilex ™...
  • Page 116 JTAG Header or Configuration JTAG Chain Pins CCIO_SDM Pin 1 VCCIO_SDM OPEN OPEN OPEN Download cable 10 pin male header (JTAG mode) Related Information Intel FPGA Download Cable II User Guide Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 117 3. Intel Agilex Configuration Schemes UG-20205 | 2019.10.09 3.4.2.2. JTAG Single-Device Configuration using a Microprocessor Refer to the Intel Agilex Device Family Pin Connection Guidelines for additional information about individual pin usage and requirements. Figure 51. Connection Setup for JTAG Single-Device Configuration using a Microprocessor...

  • Page 118: Jtag Multi-Device Configuration

    JTAG chain. • If you have four or more devices in a JTAG chain, buffer the , and pins with an on-board buffer. You can also connect other Intel FPGA devices with JTAG support to the chain. Intel ® Agilex ™...

  • Page 119: Debugging Guidelines For The Jtag Configuration Scheme

    Resistor values can vary between 1 kΩ to 10 kΩ. Connect MSEL [2:0] of Intel FPGA devices based on the non-JTAG configuration scheme. Perform signal integrity to select the resistor value for your setup. 3.4.4. Debugging Guidelines for the JTAG Configuration Scheme The JTAG configuration scheme overrides all other configuration schemes.
  • Page 120 Intel Quartus Prime Pro Edition Programmer generates for error reporting. Note: For Intel Agilex SX devices when you choose to configure the FPGA fabric first, the JTAG chain has no mechanism to redeliver the HPS boot information following a cold reset. Consequently, you must reconfig the device with the file or avoid cold .sof...

  • Page 121: Remote System Update (Rsu)

    The following figure shows functional diagrams for typical remote system update processes. Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
  • Page 122 RSU Setup Note: An Intel Agilex version of the Intel Stratix 10 SoC Remote System Update (RSU) User Guide is not yet available. The RSU SoC implementation in Intel Agilex is very similar to the implementation in Intel Stratix 10.

  • Page 123: Remote System Update Functional Description

    Firmware to identify and load the highest priority image. Previous versions of this user guide refer to decision firmware as static firmware. Starting in version 19.1 of the Intel Quartus Prime software, you can use RSU to update this firmware.

  • Page 124: Remote System Update Using As Configuration

    • Designs that do not use the HPS as the remote system update host require an Mailbox Client Intel FPGA IP as shown in the figure below. The Mailbox Client sends and receives remote system update operation commands and responses, such...

  • Page 125: Remote System Update Configuration Images

    Depending on the storage space of your flash memory, Intel Agilex remote system update supports one factory image and up to 507 application images. The Quartus Programming File Generator only supports up to seven remote system update images.

  • Page 126: Remote System Update Configuration Sequence

    Remote Update Application Application Image Application Remote Update to Application Image Images to Factory Image Image Application Image Enter User Mode Enter User Mode with Factory with Application Image Image Application Image Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 127: Rsu Recovery From Corrupted Images

    6. If loading the factory image fails, you can recover by reprogramming the quad SPI flash with the initial RSU flash image using the JTAG interface. 4.1.5. RSU Recovery from Corrupted Images When an RSU fails, the Mailbox Client Intel FPGA IP command provides information about the current RSU_STATUS configuration status, including the currently running image and most recent failing image.
  • Page 128 RSU_STATUS includes the following information: — Current_Image: Application Image0 — : records information Highest priority failing image State Version Error location Error details for Application Image3 which is the highest priority failing image. Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 129 Application Image2 - Corrupt Address Offset <O> * 64 KB Last Failing Image Application Image3 - Corrupt Highest Priority Address Offset <P> * 64 KB Failing Image Related Information Operation Commands on page 134 Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 130: Updates With The Factory Update Image

    If there are errors in the firmware or in the factory image Intel provides a safe solution for you to update the factory image and the associated decision firmware and decision firmware data remotely. The update process stores multiple copies of critical data so that if power is lost or the update is disrupted, the device is still able to restart and continue the update.

  • Page 131: Guidelines For Performing Remote System Update Functions For Non-Hps

    (SDM) Master Bridge) Here are guidelines to follow when implementing remote system update: 1. The factory or application image must at least contain a remote system update host controller and the Mailbox Client Intel FPGA IP. • You can use either custom logic, the Nios II processor, or the JTAG to Avalon Master Bridge IP as a remote system update host controller.

  • Page 132: Commands And Responses

    Block Diagram Intel FPGA IPThe following figure illustrates the role of the Mailbox Client Intel FPGA IP in a Intel Agilex design. The Mailbox Client IP enables communication with the SDM to access quad SPI flash memory and system status.
  • Page 133 Your client must read all the response words, even if your client does not interpret all the response words. Table 34. Mailbox Client Intel FPGA IP Command and Response Header Description Header Description...

  • Page 134: Operation Commands

    The 4-word response contains the following information: Offset Name Description SPT0[63:32] SPT0 address in quad SPI flash. SPT0[31:0] SPT1[63:32] SPT0 address in quad SPI flash. SPT1[31:0] continued... This number does not include the command and response header. Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 135 Contains the error location. Returns 0 if there are no errors. Error details Contains the error details. Returns 0 if there are no errors. continued... This number does not include the command and response header. Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 136 139 and Table 37 on page 140 for more information. Error Reporting and Starting with version 19.3 of the Intel Quartus Prime Pro Version Edition software, contains the following fields: • Bits[31:16]: Source of error. The following encodings are valid: —...
  • Page 137 MAX_RETRY available retries is MAX_RETRY -1 This field was added in version 19.3 of the Intel Quartus Prime Pro Edition Software. Requests exclusive access to the quad SPI. The SDM accepts the request if the quad SPI is not in QSPI_OPEN use and the SDM is not configuring the device.
  • Page 138 The number of words to write (one word). • The data to be written (one or more words). A successful write returns the OK response code. To prepare memory for writes, Intel recommends using the command before issuing QSPI_ERASE this command.
  • Page 139 • 0x00060000: Clear error status information. • All other values are reserved. This command is not available before version 19.3 of the Intel Quartus Prime Pro Edition Software. Table 36. CONFIG_STATUS and RSU_STATUS Major Error Code Descriptions Major Error Code...

  • Page 140: Error Code Responses

    • An HPS configuration failure Contact your local Field Applications Engineer (FAE). Alternatively, submit a Service Request on the My Intel support page to get the support on capturing the error log for further debug. 0xF006 HPS watchdog timeout failure. Ensure that your design resets the watchdog timer correctly.

  • Page 141: Quad Spi Flash Layout

    The firmware contains a pointer to the location of the highest priority application image in flash. Typically the application image is immediately after the four firmware copies, but the Intel Quartus Prime Pro Edition tools do not require this location.
  • Page 142 In the RSU case, decision firmware replaces the standard firmware. The decision firmware copies have pointers to the following structures in flash: • Decision data • One factory image • Two Pointer Blocks (CPBs) Direct to Factory Direct to Factory Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 143 The pointer blocks contain a list of application images to be tried until one of them is successful. If none are successful, the SDM loads the factory image. To ensure reliability, the pointer block includes a main and a backup copy in case an update operation fails. Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 144 SPT and report it to the SDM. . The Intel Quartus Prime Programming File Generator creates the SPT when creating the initial manufacturing image. To ensure reliable operation, the Programming File Generator creates two copies, sub-partition table and the configuration...
  • Page 145 You do not need to know the addresses of the decision firmware, decision firmware data, and factory image. • You have access to the sub-partition tables. The sub-partition tables provide access to the data structures required for remote system update. Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 146: Detailed Quad Spi Flash Layout

    When you create the initial flash image, you can create up to seven partitions for application images. There are no limitations on creating empty partitions. 4.4.2.2. Sub-Partition Table Layout The following table shows the structure of the sub-partition table. The Intel Quartus Prime software supports up to 126 partitions. Each sub-partition descriptor is 32 bytes. Intel ®...
  • Page 147 The structure contains the following information: Table 43. Pointer Block Layout Offset Size (in bytes) Description Magic number 0x57789609 0x00 Size of pointer block header (0x18 for this document) 0x04 continued... Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 148 • All 0’s – the entry was previously used and then canceled. • A combination of 1's and 0's – a valid pointer to an application image. Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 149 16 bytes to store a Version ID to identify your application image. Providing this Version ID allows you to verify the images stored in flash memory at a later time. Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 150 4. Recompute the CRC32 for addresses 0x1000 to 0x1FFB. Store the new value at offset 0x1FFC. The CRC32 value must be computed on a copy of the data using the following procedure: Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 151: Generating Remote System Update Image Files Using The Programming File Generator

    . 4.5. Generating Remote System Update Image Files Using the Programming File Generator Use the Intel Quartus Prime Programming File Generator tool to generate the Intel Agilex remote system update flash programming files.
  • Page 152 Input file drop-down list and click OK. .sof Note: You must assign Page 0 to Factory Image. Intel recommends that you let the Intel Quartus Prime software assign the Start address of the automatically by retaining the default value for Address Mode which is FACTORY_IMAGE Auto.

  • Page 153: Generating An Application Image

    1. On the File menu, click Programming File Generator. 2. Select Intel Agilex from the Device family drop-down list. 3. Select the configuration mode from the Configuration mode drop-down list. The current Intel Quartus Prime only supports remote system update feature in Active Serial x4.
  • Page 154 .rpd 8. On the Input Files tab, click Add Bitstream. Change the Files of type to SRAM Object File ( ). Then, select *.sof application image file and click Open. .sof Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 155: Generating A Factory Update Image

    -c fpga.sof factory_update.rpd -o mode=ASX4 -o start_address=<address> -o bitswap=ON -o rsu_upgrade=ON Alternatively, you can use the Intel Quartus Prime Pro Edition Programming File Generator to generate a factory update image ( ). You can use this image to update the decision firmware, decision firmware data, and the factory image.
  • Page 156 .rpd 8. On the Input Files tab, click Add Bitstream. Change the Files of type to SRAM Object File ( ). Then, select *.sof factory image file and click Open. .sof Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 157 UG-20205 | 2019.10.09 Figure 65. Specify the .sof File Input files to convert Add Bitstream SOF Data Generate 9. Select the and then click Properties. Turn On Remote System Firmware Update. .sof Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 158 UG-20205 | 2019.10.09 Figure 66. Turn On Remote System Firmware Upgrade Turn On 10. Click Generate to generate the RSU programming files. You can now update the Intel Agilex firmware. You can save the configuration in a file for later use. .pfg Intel ®...

  • Page 159: Remote System Update From Fpga Core Example

    ) containing the bitstreams to add an application image in user mode. .rpd 5. Adding an application image. 6. Removing an application image. 4.6.1. Prerequisites To run this remote system update example, your system must meet the following hardware and software requirements: Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 160 • Your design should include the Mailbox Client Intel FPGA IP that connects to a JTAG to Avalon Master Bridge as shown the Platform Designer system. The JTAG to Avalon Master Bridge acts as the remote system update host controller for your factory and application images.

  • Page 161: Creating Initial Flash Image Containing Bitstreams For Factory Image And One Application Image

    1. On the File menu, click Programming File Generator. 2. Select Intel Agilex from the Device family drop-down list. 3. Select the configuration mode from the Configuration mode drop-down list. The current Intel Quartus Prime Software only supports remote system update feature in Active Serial x4.
  • Page 162 4. Remote System Update (RSU) UG-20205 | 2019.10.09 6. On the Input Files tab, click Add Bitstream, select the factory and application image files and click Open. .sof Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 163 4. Remote System Update (RSU) UG-20205 | 2019.10.09 a. Bitstream_1 is the bitstream for factory image. b. Bitstream_2 is the bitstream for application image. Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 164 .sof Assign Page: 1.Keep the default settings for Address Mode. Click OK. 12. For Flash loader click Select. Select Intel Agilex from Device family list. Select AGFA014R24A3E3VR0 for the Device name. Click OK. 13. Click Generate to generate the remote system update programming files. The Programming File Generator generates the following files: Initial_RSU_Image.jic...
  • Page 165 4. Remote System Update (RSU) UG-20205 | 2019.10.09 Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 166 Quad-Serial configuration device dummy clock cycle: 15 Notes: - Data checksum for this conversion is 0xBFFB90A5 - All the addresses in this file are byte addresses After generating the programming file, you can program the flash memory. Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 167: Programming Flash Memory With The Initial Remote System Update Image

    You can program the initial remote system update image from the command line, by running the following command: quartus_pgm -c 1 -m jtag -o "pvi;./Initial_RSU_Image.jic Alternatively, you can use the Intel Quartus Prime Programmer to program the initial RSU update image by completing the following procedure: 1.
  • Page 168 4. Remote System Update (RSU) UG-20205 | 2019.10.09 Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 169 5. Use the command to determine which bitstream image the Programmer is using as shown in the following RSU_STATUS example: a. In the Intel Quartus Prime software, select Tools System Debugging Tools System Console to launch the system console. b. In the Tcl Console pane, type to open the example of Tcl script to perform the remote system source rsu1.tcl...
  • Page 170 4. Remote System Update (RSU) UG-20205 | 2019.10.09 Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 171: Reconfiguring The Device With An Application Or Factory Image

    2. In the Tcl console of the System Console, type to verify the current image. The following figure shows the rsu_status device is being reconfigured with the factory image. Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 172: Adding An Application Image

    QSPI_CLOSE command. QSPI_WRITE 2. Alternatively, the script includes the function that programs a new application image into rsu1.tcl program_flash flash memory. The following command accomplishes this task: program_flash new_application_image.rpd 0x03FF0000 1024 Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 173 CPB0 and CPB1 must point to the start address of the 0x20 application image. The next new image pointer entry value must be before you write the start address of the 0xFFFFFFFF new application image to the next image pointer entry. Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 174 You can use the function verify that the new image pointer entry value is . The function QSPI_read 0xFFFFFFFF QSPI_read takes in two arguments: 1. Start address 2. Number of words to read Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 175 You can now proceed to write the new application image address to next image entry by using the QSPI_write_one_word function. The function takes in two arguments: QSPI_write_one_word 1. Address 2. The value of the word Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 176 QSPI_read the desired new application image. Verifying the Update to the New Image Pointer entry at 0x00234028 Host software can now reconfigure the Intel Agilex FPGA with the new application image by asserting the pin. nCONFIG Alternatively, you can power cycle the PCB. After reconfiguration, check the current image address. The expected address is .

  • Page 177: Removing An Application Image

    CPB0 + 0x28 0x002E4028 0x03FF0000 (highest priority) CPB1 + Old application image pointer entry (lower priority) 0x20 0x002EC020 0x002F4000 Current/New application image pointer entry CPB1 + 0x28 0x002EC028 0x03FF0000 (highest priority) Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 178 QSPI_write_one_word just removed from flash memory. You can use a to the image pointer entry at offset for CBP0 and CPB1 to verify completion of the QSPI_read 0x28 commands . QSPI_write_one_word Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 179 You can now configure the device with the old application image. The old application image has the highest priority if you power cycle the device or the host asserts the pin. You can run the report to check the status of nCONFIG rsu_status the current image address, 0x002f4000 Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 180: Intel Agilex Configuration Features

    Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
  • Page 181 5. Intel Agilex Configuration Features UG-20205 | 2019.10.09 Figure 70. Intel Agilex CvP Configuration Block Diagram Intel FPGA CVP_CONFDONE (optional) CCIO_SDM Configuration 10kΩ 10kΩ Control Signals nCONFIG nSTATUS Optional CONF_DONE Monitoring INIT_DONE OSC_CLK_1 MSEL MSEL[2:0] Configuration Control Signals FPGA Fabric...

  • Page 182: Partial Reconfiguration

    This methodology is effective in systems with multiple functions that time-share the same FPGA device resources. PR enables the implementation of more complex FPGA systems. Related Information Intel Quartus Prime Pro Edition User Guide: Partial Reconfiguration Intel ®...

  • Page 183: Intel Agilex Debugging Guide

    Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.

  • Page 184: Intel Agilex Configuration Architecture Overview

    25, 100, or 125 MHz? OSC_CLK_1 For Intel Agilex SX parts ensure that the HPS and EMIF IOPLL are stable and free running before configuration begins. The actual frequency should match the setting specified in Platform Designer.

  • Page 185: Configuration File Format Differences

    The firmware section is not part of the file. The Intel Quartus Prime Pro Edition Programmer adds the firmware to .sof . The programmer adds the firmware when configuring an Intel Agilex device or when it converts the .sof .sof another format.

  • Page 186: Understanding Seus

    6.5. Reading the Unique 64-Bit CHIP ID he Chip ID Intel FPGA IP in each Intel Agilex device stores a unique 64-bit chip ID. Refer to the Mailbox Avalon ST Client IP User Guide learn how to read the Chip ID from the Intel Agilex device.

  • Page 187: Understanding And Troubleshooting Configuration Pin Behavior

    Internal Oscillator option in the Intel Quartus Prime. OSC_CLK_1 • Try configuring the Intel Agilex device with a simple design that does not contain any IP. If configuration via a non-JTAG scheme fails with a simple design, try JTAG configuration with the pins set specifically to JTAG.

  • Page 188: Nconfig

    The configuration source can only change the state of the pin when it has the same value as . When the nCONFIG nSTATUS Intel Agilex device is ready it drives to follow nSTATUS nCONFIG The host should drive low to initiate device cleaning. Then the host should deassert initiate configuration.

  • Page 189: Conf_Done And Init_Done

    , weak internal pull-downs pull these pins low at power-on reset. Ensure you specify INIT_DONE SDM_IO16 SDM_IO0 these pins in the Intel Quartus Prime Software or in the Intel Quartus Prime settings file, ( .qsf CONF_DONE are low prior to and during configuration.

  • Page 190: Sdm_Io Pins

    6. Intel Agilex Debugging Guide UG-20205 | 2019.10.09 are optional signals. You can use these pins for other functions that the Intel Quartus Prime Pro CONF_DONE INIT_DONE Edition Device and Pin Options menu defines. Debugging Suggestions Place the pins on the pins that correlate with the board-level connection.
  • Page 191 6. Intel Agilex Debugging Guide UG-20205 | 2019.10.09 Figure 72. Configuration Pin Selection in the Intel Quartus Prime Pro Edition Software Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 192 6. Intel Agilex Debugging Guide UG-20205 | 2019.10.09 Figure 73. Fitter Report and SDM_IO Pin Reporting Starting with the Intel Quartus Prime Pro Edition Software, version 18.1, an SDM Debug Toolkit is available through the System Console, Tools System Debugging Tools System Console Intel Agilex SDM Debug Toolkit.

  • Page 193: Intel Agilex Configuration User Guide Archives

    Intel Agilex Configuration User Guide Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.

  • Page 194: Document Revision History For The Intel Agilex Configuration User Guide

    Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
  • Page 195 Power Management & VID Slave device type. • Corrected maximum speed and data rate in the Intel Agilex Configuration Data Width, Clock Rates, and Data Rates table. The Max Clock Rate is 33 MHz. The Max Data Rate is 33 Mbps. •...
  • Page 196 8. Document Revision History for the Intel Agilex Configuration User Guide UG-20205 | 2019.10.09 Document Version Intel Quartus Changes Prime Version • Removed vector for in the Configuration, Reconfiguration, and Error Timing Diagram figure. Power_Supply_Status • Corrected the Intel Agilex FPGA Configuration Flow diagram. The transition between...

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