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8XC196K x, J x , CA USER'S MANUAL
CCR1
CCR1 (Continued)
The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode.
Two of its bits combine with three bits of CCR0 to control wait states and bus width.
7
CA, J x , KQ, KR
7
KS, KT
MSEL1
Bit
Bit
Number
Mnemonic
1
IRC2
0
—
C-32
1
1
0
MSEL0
0
Ready Control
This bit, along with IRC0 (CCR0.4) and IRC1 (CCR0.5), limits the number
of wait states that can be inserted while the READY pin is held low. Wait
states are inserted into the bus cycle either until the READY pin is pulled
high or until this internal number is reached.
IRC2 IRC1 IRC0
0
0
0
0
X
1
0
1
X
1
0
0
1
0
1
1
1
0
1
1
1
†
This mode is unavailable on the 8XC196J x device. On this device, the
READY pin is not implemented. Therefore, the number of wait states
inserted into the bus cycle is determined only by the IRC2:0 bit settings.
Reserved; always write as zero.
1
WDE
BW1
1
WDE
BW1
Function
zero wait states
illegal
illegal
one wait state
two wait states
three wait states
†
infinite
Address:
201AH
Reset State:
XXH
IRC2
0
IRC2
0
0
0
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