Disabling The Bus-Hold Protocol (8Xc196K X Only); Hold Latency (8Xc196K X Only) - Intel 8XC196K Series User Manual

You must also set the hold enable bit (HLDEN) in the window selection register (WSR.7) to en-
able the bus-hold protocol. Once the bus-hold protocol has been selected, the port functions of
P2.3, P2.5, and P2.6 cannot be selected without resetting the device. (During the time that the pins
are configured to operate as special-function signals, their special-function values can be read
from the P2_PIN.x bits.) However, the hold function can be dynamically enabled and disabled as
described in "Disabling the Bus-hold Protocol (8XC196Kx Only)."

15.5.2 Disabling the Bus-hold Protocol (8XC196K x Only)

To disable hold requests, clear WSR.7. The device does not take over the bus immediately after
HLDEN is cleared. Instead, it waits for the current HOLD# request to finish and then disables the
bus-hold feature and ignores any new requests until the bit is set again.
Sometimes it is important to prevent another device from taking control of the bus while a block
of code is executing. One way to protect a code segment is to clear WSR.7 and then execute a
JBC instruction to check the status of the HLDA# signal. The JBC instruction prevents the RALU
from executing the protected block until current HOLD# requests are serviced and the hold fea-
ture is disabled. This is illustrated in the following code:
DI
PUSH WSR
LDB WSR,#1FH
WAIT: JBC P2_PIN,6, WAIT
POP WSR
EI

15.5.3 Hold Latency (8XC196K x Only)

When an external device asserts HOLD#, the device finishes the current bus cycle and then as-
serts HLDA#. The time it takes the device to assert HLDA# after the external device asserts
HOLD# is called hold latency (see Figure 15-8). Table 15-4 lists the maximum hold latency for
each type of bus cycle.
Internal execution or idle mode
16-bit external execution
8-bit external execution
;Disable interrupts to prevent
;code interruption
;Disable hold requests and
;window Port 2
;Check the HLDA# signal. If set,
;add protected instruction here
;Enable hold requests
;Enable interrupts
Table 15-4. Maximum Hold Latency
Bus Cycle Type
INTERFACING WITH EXTERNAL MEMORY
Maximum Hold Latency
(state times)
1.5
2.5 + 1 per wait state
2.5 + 2 per wait state
15-19