Intel Agilex Configuration User Manual
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Intel Agilex Configuration User Manual

Intel Agilex Configuration User Manual

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Configuration User Guide
UG-20205 | 2019.04.03
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  • Page 1 ® ™ Intel Agilex Configuration User Guide ® ® Updated for Intel Quartus Prime Design Suite: 19.1 Subscribe UG-20205 | 2019.04.03 Send Feedback Latest document on the web: HTML...

  • Page 2: Table Of Contents

    3.1.4. Avalon-ST Single-Device Configuration.......................40 3.1.5. Debugging Guidelines for the Avalon-ST Configuration Scheme................43 3.1.6. IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core....... 44 3.2. AS Configuration.................................53 3.2.1. AS Configuration Scheme Hardware Components and File Types ................54 3.2.2.
  • Page 3 5.4. Remote System Update Flash Device Layout........................97 5.4.1. Configuration Firmware Pointer Block (CPB)......................98 6. Intel Agilex Debugging Guide............................... 99 6.1. Configuration Debugging Checklist..........................99 6.2. Intel Agilex Configuration Architecture Overview......................100 6.3. Configuration Pin Differences from Previous Device Families....................101 Intel ®...
  • Page 4 6.6. Reading the Unique 64-Bit CHIP ID..........................104 6.7. Understanding and Troubleshooting Configuration Pin Behavior..................104 6.7.1. nCONFIG..............................105 6.7.2. nSTATUS..............................106 6.7.3. CONF_DONE and INIT_DONE..........................107 7. Document Revision History for the Intel Agilex Configuration User Guide................108 Intel ® Agilex ™...

  • Page 5: Intel ® Agilex ™ Configuration Overview

    Secure Digital and Multi Media Card (SD/MMC) Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
  • Page 6 MSEL CvP uses an external PCIe* host device as a Root Port to configure the Intel Agilex device over the PCIe link. You can specify up to a x16 PCIe link. Intel Agilex devices support two CvP modes, CvP init and CvP update.
  • Page 7 In AS fast mode, the SDM first powers the external AS x4 flash. The power supply must be able to provide an equally fast ramp up for the Intel Agilex device and the external AS x4 flash devices. Failing to meet this requirement causes the SDM to assume the memory is missing .

  • Page 8: Configuration And Related Signals

    AS x4. The advantages of this mode are cost, capacity, availability, portability, and compatibility. Because Intel Agilex devices operate at 1.8 volt an intermediate voltage level shifter may be required to interface with the higher voltage I/Os in SD/MMC devices.

  • Page 9: Intel Download Cables Supporting Configuration In Intel Agilex Devices

    1.1.2. Intel Download Cables Supporting Configuration in Intel Agilex Devices Intel provides the following cables to download your design to the Intel Agilex device on the PCB. Download cables support prototyping activity by providing detailed debug messages via Intel Quartus Prime Programmer. You must use Intel download cables for advanced debugging using the Signal Tap logic analyzer or the System Console tools.

  • Page 10: Intel Agilex Configuration Architecture

    The Secure Device Manager (SDM) is a triple-redundant processor-based module that manages configuration and the security features of Intel Agilex devices. The SDM is available on all Intel Agilex FPGAs and SoC devices. The block diagram below provides an overview of the Intel Agilex configuration architecture which includes the following blocks: •...

  • Page 11: Secure Device Manager

    Configuration bitstream authentication: After power-on during startup, the SDM triple-redundant lockstep processors run product="s10 code from the boot ROM. The boot ROM code authenticates the Intel-generated configuration firmware and configuration bitstream, ensuring that configuration bitstream is from a trusted source.
  • Page 12 UG-20205 | 2019.04.03 Note: These security features are available in Intel Agilex devices that support advanced security. The ordering codes for Intel Agilex devices that include advanced security features includes the AS (Advanced Security) suffix. Contact your Intel Programmable Solutions representative to get additional information about Intel Agilex device security features.
  • Page 13 1.2.1.1. Specifying Boot Order for Intel Agilex SoC Devices For Intel Agilex SoC devices you can specify the configuration order, choosing either the FPGA First or the Hard Processor System (HPS) First options. When you select the FPGA First option, the SDM fully configures the FPGA, then configures the HPS SDRAM pins, loads the HPS first stage boot loader (FSBL) and takes the HPS out of reset.

  • Page 14: Intel Agilex Configuration Details

    Down Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
  • Page 15 19 to hold your application logic in the reset state until the entire FPGA fabric is in user mode. Failure to include this IP in your design may result in intermittent application logic failures. Reconfiguration Timing The second event the timing diagram illustrates the Intel Agilex device reconfiguration. If you change the setting after MSEL power-on, you must power-cycle the Intel Agilex.
  • Page 16 Power Supply Status The power-on reset (POR) holds the Intel Agilex device in the reset state until the power supply outputs are within the recommended operating range. defines the maximum power supply ramp time. If POR does not meet the...

  • Page 17: Configuration Flow Diagram

    ± Power Up • The Intel Agilex power supplies power following the guidelines in the Power-Up Sequence Requirements for Intel Agilex Devices section of the Intel Agilex Power Management User Guide. • A device-wide power-on reset (POR) asserts after the power supplies reach the correct operating voltages. The external power supply ramp must not be slower than the minimum ramping rate until the supplies reach the operating voltage.
  • Page 18 2. Intel Agilex Configuration Details UG-20205 | 2019.04.03 SDM Startup • The SDM samples the pins during power-on. MSEL • is set to JTAG, the SDM remains in the Startup state. MSEL • The SDM runs firmware stored in the on-chip boot ROM and enters the Idle state until the host drives high.

  • Page 19: Intel Agilex Reset Release Ip

    Intel strongly recommends that you use Intel Agilex Reset Release IP in your design to provide a known initialized state for your logic to begin operation. The Reset Release IP is available in the Intel Quartus Prime Software, version 19.1 and later . This IP consists of a single output signal, .
  • Page 20 Consequently, the IP does not nINIT_DONE consume any FPGA fabric resources, but does require routing resources. You can find the Reset Release IP in the Intel Quartus Prime and Platform Designer IP Catalogs under Basic Functions/Configuration and Programming. Figure 6.

  • Page 21: Additional Clock Requirements For Transceivers, Hps, Pcie, And Emif

    The Intel Agilex device has additional clock requirements for transceivers, the HPS, PCIe, and External Memory Interface (EMIF) IP. For successful configuration, the Intel Agilex device requires additional clocks for transceivers, the HPS, PCIe, and EMIF IP. You must provide a free-running, stable reference clock to these blocks before configuration begins. This reference clock is in...

  • Page 22: Intel Agilex Configuration Pins

    2.5. Intel Agilex Configuration Pins The Intel Agilex device uses SDM pins for device configuration. 2.5.1. SDM Pin Mapping You can use SDM pins for configuration and other functions such as power management and SEU detection. You specify SDM...
  • Page 23 The GPIO pin assignments are fixed. The SDM I/O pin assignments are flexible. You assign SDM I/O pin functions using the Device Configuration Device and Pin Options dialog box in the Intel Quartus Prime software. The following table lists the possible pin assignments for configuration functions that you can assign to SDM I/O pins. Table 4.
  • Page 24 2. Intel Agilex Configuration Details UG-20205 | 2019.04.03 Configuration Scheme Signal Names Avalon-ST AS x4 SDM_IO9 SDM_IO9 SDM_IO12 SDM_IO12 SDM_IO12 SDM_IO12 CONF_DONE SDM_IO0 SDM_IO0 SDM_IO0 SDM_IO0 SDM_IO5 SDM_IO1 SDM_IO1 SDM_IO10 SDM_IO12 SDM_IO2 SDM_IO2 SDM_IO11 SDM_IO16 SDM_IO3 SDM_IO3 SDM_IO12 SDM_IO4 SDM_IO4...
  • Page 25 2. Intel Agilex Configuration Details UG-20205 | 2019.04.03 Configuration Scheme Signal Names Avalon-ST AS x4 SDM_IO14 SDM_IO14 SDM_IO15 SDM_IO15 SDM_IO16 SDM_IO16 Not supported Not supported CVP_CONFDONE SDM_IO0 SDM_IO0 SDM_IO5 SDM_IO10 SDM_IO7 SDM_IO11 SDM_IO9 SDM_IO12 SDM_IO12 SDM_IO13 SDM_IO16 SDM_IO14 SDM_IO15 SDM_IO16...
  • Page 26 2. Intel Agilex Configuration Details UG-20205 | 2019.04.03 Configuration Scheme Signal Names Avalon-ST AS x4 SDM_IO9 SDM_IO3 SDM_IO3 SDM_IO12 SDM_IO12 SDM_IO4 SDM_IO4 SDM_IO13 SDM_IO16 SDM_IO5 SDM_IO5 SDM_IO14 SDM_IO6 SDM_IO6 SDM_IO15 SDM_IO7 SDM_IO7 SDM_IO16 SDM_IO9 SDM_IO9 SDM_IO10 SDM_IO10 SDM_IO11 SDM_IO11 SDM_IO12...

  • Page 27: Msel Settings

    SDM_IO14 SDM_IO15 SDM_IO15 SDM_IO16 SDM_IO16 2.5.2. MSEL Settings pins set the configuration scheme for Intel Agilex devices. Use 4.7-kΩ resistors to pull the pins MSEL[2:0] MSEL[2:0] up to V or down to ground as required by the setting for configuration scheme.

  • Page 28: Device Configuration Pins

    If you use AS Fast mode and are not concerned about 100 ms PCIe linkup, you must still ramp the supply within 18 ms. CCIO_SDM This ramp-up requirement ensures that the AS x4 device is within its operating voltage range when the Intel Agilex device begins to access it. JTAG configuration works with any settings, unless disabled for security.
  • Page 29 SDM I/O pins to the configuration pins without dedicated pin assignments. You can only use GPIOs for PR_REQUEST , and pins by specifying them in the Intel Quartus Prime software and connecting them to the Partial PR_ERROR PR_DONE Reconfiguration External Configuration Controller Intel Agilex FPGA IP.
  • Page 30 CCIO_SDM SD/MMC Output SDMMC_CFG_CCLK CCIO_SDM Note: To avoid false signaling indicating successful configuration, Intel recommends that you include an external weak pull-down resistor for pins. CONF_DONE INIT_DONE You enable the pin function in the Intel Quartus Prime Software. The Avalon-ST configuration scheme using the Parallel CONF_DONE Flash Loader (PFL) II requires this pin.
  • Page 31 SDM pins are also available for the SmartVID power management feature for -V devices. You must also set the correct Power Management Bus (PMBus) settings when using the SmartVID feature. Refer to the Intel Agilex Power Management User Guide for more information about the pin assignments and PMBus setting.

  • Page 32: Configuration Clocks

    — AVST_DATA GPIO bank You can download the IBIS models from the IBIS Models for Intel Devices web page. The Intel Quartus Prime software does not support IBIS model generation for configuration pins in the current release. Unused SDM Pins You can specify other functions on unused SDM pins in the Intel Quartus Prime software.
  • Page 33 250 MHz clock for configuration. Using OSC_CLK_1 source enables the fastest possible configuration. Refer to Setting Configuration Clock Source for instructions OSC_CLK_1 setting this frequency using the Intel Quartus Prime Software. Intel ® Agilex ™...

  • Page 34: Intel Agilex Configuration Schemes

    FPGA. The design that controls the configuration process resides in the external host. You can use the PFL II IP with a MAX II, MAX V, or Intel MAX 10 device as the host to read configuration data from the flash memory device and configure the Intel Agilex device.

  • Page 35: Avalon-St Configuration Scheme Hardware Components And File Types

    A custom host, typically a microprocessor, with any external memory • The Intel FPGA Download Cable II to connect the Intel Quartus Prime Programmer to the PCB. The following block diagram illustrates the components and design flow using the Avalon-ST configuration scheme.

  • Page 36: The Avst_Ready Signal

    The configuration files for Intel Agilex devices can be highly compressed. During configuration, the decompression of the bit stream inside the device requires the host to pause before sending more data. The Intel Agilex device asserts the signal when the device is ready to accept data. The...
  • Page 37 Perform timing analysis on both signals AVST_CLK AVST_DATA between the host and Intel Agilex device to ensure the Avalon-ST configuration timing specifications are met. Refer to the Avalon-ST Configuration Timing section of the Intel Agilex Device Data Sheet for information about the timing specifications. Note: signal must run continuously during configuration.
  • Page 38 If you use the PFL II IP core as the configuration host, you can use the Intel Quartus Prime software to store the binary configuration data to the flash memory through the PFL II IP core.

  • Page 39: Rbf Configuration File Format

    3. Intel Agilex Configuration Schemes UG-20205 | 2019.04.03 3.1.3. RBF Configuration File Format If you do not use the Parallel Flash Loader II Intel FPGA IP core to program the flash, you must generate the file. .rbf The data in file are in little-endian format .rbf...

  • Page 40: Avalon-St Single-Device Configuration

    3. Intel Agilex Configuration Schemes UG-20205 | 2019.04.03 3.1.4. Avalon-ST Single-Device Configuration Figure 11. Connections for Avalon-ST x8 Single-Device Configuration Configuration CCIO_SDM External Host Control Signals Intel FPGA CPLD / FPGA 10kΩ fpga_nconfig nCONFIG fpga_nstatus nSTATUS fpga_conf_done CONF_DONE INIT_DONE Parallel Flash Loader II IP...
  • Page 41 3. Intel Agilex Configuration Schemes UG-20205 | 2019.04.03 Figure 12. Connections for Avalon-ST x16 Single-Device Configuration CCIO_SDM External Host Configuration Control Signals Intel FPGA CPLD / FPGA 10kΩ nCONFIG fpga_nconfig nSTATUS fpga_nstatus CONF_DONE fpga_conf_done INIT_DONE Parallel Flash Loader II IP...
  • Page 42 3. Intel Agilex Configuration Schemes UG-20205 | 2019.04.03 Figure 13. Connections for Avalon-ST x32 Single-Device Configuration External Host CCIO_SDM Configuration Control Signals Intel FPGA CPLD / FPGA 10kΩ nCONFIG fpga_nconfig nSTATUS fpga_nstatus CONF_DONE fpga_conf_done INIT_DONE Parallel Flash Loader II IP...

  • Page 43: Debugging Guidelines For The Avalon-St Configuration Scheme

    3. Intel Agilex Configuration Schemes UG-20205 | 2019.04.03 Notes for Figure: 1. Refer to MSEL Settings for the correct resistor pull-up and pull-down values for all configuration schemes. 2. The pins are dual-purpose. After power-on, you can reassign these pins to other functions. For more information,...

  • Page 44: Ip For Use With The Avalon-St Configuration Scheme: Intel Fpga Parallel Flash Loader Ii Ip Core

    3.1.6. IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core 3.1.6.1. Functional Description You can use the Parallel Flash Loader II Intel FPGA IP (PFL II) with an external host, such as the MAX II, MAX V, or Intel MAX 10 devices to complete the following tasks: •...
  • Page 45 You have JTAG or In-System Programming (ISP) access to the configuration host. • You want to program the flash memory device with non-Intel FPGA data, for example initialization storage for an ASSP. You can use the PFL II IP core to program the flash memory device for the following purposes: —...
  • Page 46 3. Intel Agilex Configuration Schemes UG-20205 | 2019.04.03 Figure 16. Flash Memories in 16-Bit Mode The flash memory addresses in 16-bit flash memory shift one bit down in comparison with the flash addresses in PFL II IP core. The flash address in the flash memory starts from bit 1 instead of bit 0.
  • Page 47 0×2000 • Auto mode—allows the Intel Quartus Prime software to automatically determine the start address of the page. The Intel Quartus Prime software aligns the pages on a 128 KB boundary. If the first valid start address is , the next valid...
  • Page 48 3. Intel Agilex Configuration Schemes UG-20205 | 2019.04.03 3.1.6.2. PFL II Parameters Table 12. PFL II General Parameters Options Value Description What operating mode • Flash Programming Specifies the operating mode of flash programming and FPGA configuration control in one will be used? IP core or separate these functions into individual blocks and functionality.
  • Page 49 Specifies the flash access time. This information is available from the flash datasheet. access time? Intel recommends specifying a flash access time that is equal to or greater than the required time. For CFI parallel flash, the unit is in ns. For NAND flash, the unit is in μs. NAND flash uses pages instead of bytes and requires greater access time.
  • Page 50 Intel Burst mode • Normal mode—applicable for all flash memory • 16 byte page mode (GL only) • Intel Burst mode—Applicable for devices that support bursting. Reduces sequential • 32 byte page mode (MT23EW) read access time • Micron Burst Mode (M58BW) •...
  • Page 51 3. Intel Agilex Configuration Schemes UG-20205 | 2019.04.03 3.1.6.3. PFL II Signals Table 16. PFL II Signals Type Weak Pull-Up Function Input — Asynchronous reset for the PFL II IP core. Pull high to enable FPGA pfl_nreset configuration. To prevent FPGA configuration, pull low when you do not use the PFL II IP core.
  • Page 52 Do not connect these pins from the flash memory device to the host if you are not using burst mode. continued... Intel recommends that you do not insert logic between the PFL II pins and the host I/O pins, especially on the flash_data pins.

  • Page 53: As Configuration

    3.2. AS Configuration In AS configuration schemes, the SDM block in the Intel Agilex device controls the configuration process and interfaces. The serial flash configuration device stores the configuration data. During AS Configuration, the SDM first powers on with the boot ROM.

  • Page 54: As Configuration Scheme Hardware Components And File Types

    • Quad SPI flash memory • The Intel FPGA Download Cable II to connect the Intel Quartus Prime Programmer to the PCB. The following block diagram illustrates the components and design flow using the AS configuration scheme. Figure 19. Components and Design Flow for .jic Programming...
  • Page 55 Programming File Type Extension Description JTAG Indirect Configuration File enables serial flash programming via Intel FPGA JTAG pins. This file type is available .jic .jic only for AS configuration. Before programming the flash, the Programmer configures the FPGA with the Serial Flash Helper Design.

  • Page 56: As Single-Device Configuration

    3. Intel Agilex Configuration Schemes UG-20205 | 2019.04.03 3.2.2. AS Single-Device Configuration Figure 20. Connections for AS x4 Single-Device Configuration CCIO_SDM Configuration 10kΩ Control Signals 10kΩ Intel FPGA nCONFIG nSTATUS Optional CONF_DONE Monitoring INIT_DONE Optional OSC_CLK_1 MSEL MSEL[2:0] CCIO_SDM Pin 1...

  • Page 57: As Using Multiple Serial Flash Devices

    UG-20205 | 2019.04.03 3.2.3. AS Using Multiple Serial Flash Devices Intel Agilex devices support one AS x4 flash memory device for AS configuration and up to three AS x4 flash memories for use with HPS data storage. The pins are dual-purpose and operate as only during POR state.
  • Page 58 3. Intel Agilex Configuration Schemes UG-20205 | 2019.04.03 Figure 21. Connections for AS Configuration with Multiple Serial Flash Devices CCIO_SDM Configuration 10kΩ Control Signals 10kΩ Intel FPGA nCONFIG nSTATUS Optional CONF_DONE Monitoring INIT_DONE Optional OSC_CLK_1 MSEL MSEL[2:0] CCIO_SDM Configuration Pin 1...

  • Page 59: As Configuration Timing Parameters

    3. Intel Agilex Configuration Schemes UG-20205 | 2019.04.03 Note: When using multiple flash devices, the clock frequency must be reduced. Refer to the Intel Agilex Device Datasheet for more information. Related Information • MSEL Settings on page 27 • Intel Agilex Device Data Sheet 3.2.4.

  • Page 60: Programming Serial Flash Devices

    The capacitance loading of the flash device The table below lists the maximum allowable skew delay depending on the AS_CLK frequency. Intel recommends that you to perform IBIS simulations to ensure that the skew delay does not exceed the maximum delay specified in this table.
  • Page 61 3. Intel Agilex Configuration Schemes UG-20205 | 2019.04.03 Figure 24. AS Programming Using Intel Quartus Prime or Third-Party Programmer CCIO_SDM 10 kΩ 10 kΩ Intel FPGA AS x4 Flash External clock source nSTATUS to is optional. nCONFIG CONF_DONE DATA0 AS_DATA[0]...
  • Page 62 3. Intel Agilex Configuration Schemes UG-20205 | 2019.04.03 3.2.6.2. Programming Serial Flash Devices using the JTAG Interface The Intel Quartus Prime Programmer interfaces to the SDM device through JTAG interface and programs the serial flash device. The SDM emulates AS programming. Figure 25.
  • Page 63 AS fast mode: Pull MSEL [1] low using 4.7 kΩ resistor AS normal mode: Pull MSEL [1] high using 4.7 kΩ resistor Intel recommends using the JTAG interface to prepare the Quad SPI flash device for later use in AS mode. Intel ® Agilex ™...

  • Page 64: Serial Flash Memory Layout

    3. The programmer first configures the SDM with configuration firmware. Then, the SDM drives configuration data from the programmer to the AS x4 flash device using SDM_IOs. 4. To use the Intel Agilex device in AS mode after successful programming of the flash device, set the pins to either AS MSEL fast or AS normal mode and power cycle the device.

  • Page 65: As_Clk

    Once loaded, the SDM configures the Quad SPI flash to operate in 4-byte addressing mode and continues to load the rest of the bitstream until configuration completes. Intel Agilex devices support the following third-party flash devices operating at 1.8 V: •...

  • Page 66: Debugging Guidelines For The As Configuration Scheme

    AS_nCS0 AS_nCS3 to JTAG. If is either AS fast or normal, the SDM drives the AS pins until you power cycle the Intel Agilex device. MSEL MSEL Unlike earlier device families, the AS pins are not tristated when the device enters user mode.
  • Page 67 V supply within 18 ms. This ramp-up requirement ensures that the AS x4 device is CCIO_SDM within its operating voltage range when the Intel Agilex device begins to access it. • Check endianness of the if using a third-party programmer to program Quad SPI device.

  • Page 68: Configuration From Sd/Mmc

    SD or MMC controller to interface to the memory cards. The SDM block reads the configuration data from the memory cards for the configuration process. The configuration from SD and MMC supports x4 SD memory cards and x8 MMC. Table 21. Intel Agilex Configuration Data Width, Clock Rates, and Data Rates Mode Data Width (bits)

  • Page 69: Sd/Mmc Single-Device Configuration

    3. Intel Agilex Configuration Schemes UG-20205 | 2019.04.03 3.3.1. SD/MMC Single-Device Configuration Figure 28. Connections for SD/MMC Single-Device Configuration CCIO_SDM Configuration 10kΩ Control Signals 10kΩ Intel FPGA nCONFIG nSTATUS Optional CONF_DONE Monitoring INIT_DONE Optional OSC_CLK_1 MSEL MSEL[2:0] Configuration Control Signals...

  • Page 70: Jtag Configuration

    .sof .sof JTAG programmer to configure the Intel Agilex device. The Intel FPGA Download Cable II and the Intel FPGA Ethernet Cable both can support the V supply at 1.8 V. Alternatively, you can use the Jam*STAPL Format File ( ) or Jam Byte .jam...

  • Page 71: Jtag Configuration Scheme Hardware Components And File Types

    3. Intel Agilex Configuration Schemes UG-20205 | 2019.04.03 3.4.1. JTAG Configuration Scheme Hardware Components and File Types Figure 29. JTAG Configuration Scheme Quartus Prime Compilation Intel FPGA Quartus Prime Programmer JTAG Programmer Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 72: Jtag Device Configuration

    The configuration data is available on the pin one clock cycle later. You can configure the Intel Agilex device through JTAG using a download cable or a microprocessor. Intel ® Agilex ™...
  • Page 73 JTAG Header or Configuration JTAG Chain Pins CCIO_SDM Pin 1 VCCIO_SDM OPEN OPEN OPEN Download cable 10 pin male header (JTAG mode) Related Information Intel FPGA Download Cable II User Guide Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 74: Jtag Multi-Device Configuration

    3. Intel Agilex Configuration Schemes UG-20205 | 2019.04.03 3.4.2.2. JTAG Single-Device Configuration using a Microprocessor Figure 32. Connection Setup for JTAG Single-Device Configuration using a Microprocessor CCIO_SDM Configuration 10kΩ Control Signals Intel FPGA nCONFIG nSTATUS Optional CONF_DONE Monitoring INIT_DONE Optional...
  • Page 75 For JTAG in conjunction with another configuration scheme: Resistor values can vary between 1 kΩ to 10 kΩ. Connect MSEL [2:0] of Intel FPGA devices based on the non-JTAG configuration scheme. Perform signal integrity to select the resistor value for your setup. Intel ®...

  • Page 76: Debugging Guidelines For The Jtag Configuration Scheme

    Intel Quartus Prime Pro Edition Programmer generates for error reporting. Note: For Intel Agilex SX devices when you choose to configure the FPGA fabric first, the JTAG chain has no mechanism to redeliver the HPS boot information following a cold reset. Consequently, you must reconfig the device with the file or avoid cold .sof...
  • Page 77 • When you use the JTAG interface for reconfiguration after an initial reconfiguration using AS or the Avalon-ST interface, must be in the file format you specified in the Intel Quartus Prime project. For example, if initially configure the .sof...

  • Page 78: Intel Agilex Configuration Features

    Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
  • Page 79 4. Intel Agilex Configuration Features UG-20205 | 2019.04.03 Figure 34. Intel Agilex CvP Configuration Block Diagram Intel FPGA CVP_CONFDONE (optional) CCIO_SDM Configuration 10kΩ 10kΩ Control Signals nCONFIG nSTATUS Optional CONF_DONE Monitoring INIT_DONE OSC_CLK_1 MSEL MSEL[2:0] Configuration Control Signals FPGA Fabric...

  • Page 80: Partial Reconfiguration

    This methodology is effective in systems with multiple functions that time-share the same FPGA device resources. PR enables the implementation of more complex FPGA systems. Related Information Intel Quartus Prime Pro Edition User Guide: Partial Reconfiguration Intel ®...

  • Page 81: Remote System Update

    Using remote system update, you use the Intel Agilex Serial Flash Mailbox Client Intel FPGA IP core to write configuration bitstreams to the AS x4 flash device. Then you can use the Mailbox Client Intel Agilex FPGA IP core to instruct the SDM to reboot from the updated image.
  • Page 82 Data Remote Connection Flash Development Data Memory Location Data System Board Remote Connection Intel FPGA Active FPGA Configuration Flash Memory RSU Setup Related Information Remote Update Intel FPGA IP User Guide Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 83: Remote System Update Functional Description

    • Designs that do not use the HPS as the remote system update host require an Intel Agilex Mailbox Client FPGA IP core as shown in the figure below. The Mailbox Client sends and receives remote system update operation commands and responses.

  • Page 84: Remote System Update Configuration Images

    Depending on the storage space of your flash memory, Intel Agilex remote system update supports one factory application image and up to 507 application images. The Quartus Programming File Generator only supports up to three remote system update images.

  • Page 85: Remote System Update Configuration Sequence

    Pointers to (Primary) Remote Update to Application Application Image to Factory Image Image Application Image Image Enter User Mode Enter User Mode (Secondary) with Factory with Application Image Image Application Image N Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 86: Rsu Recovery From Corrupted Images

    6. If loading the factory image fails, you can recover by reprogramming the Quad SPI flash with the RSU image using the JTAG interface. 5.1.4. RSU Recovery from Corrupted Images When an RSU fails, the Mailbox Client Intel Agilex IP command provides information about the current RSU_STATUS configuration status, including the currently running image and most recent failing image.
  • Page 87 RSU_STATUS includes the following information: — Current_Image: Application Image0 — record information for Application Last failing image State Version Error location Error details Image3 which is the highest priority failing image. Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 88: Update Of Static Firmware And Factory Image

    In rare instances you may need to update the static firmware or factory Image, An update may be required for the following reasons: • If there are vulnerabilities in the firmware • If there are errors in the firmware or in the factory image Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 89: Guidelines For Performing Remote System Update Functions For Non-Hps

    5. Remote System Update UG-20205 | 2019.04.03 Intel provides a safe solution for you to update the static firmware and factory image remotely, Here are the steps to perform the update: 1. Generate the update Image using Programming File Generator, This bitstream consists of both new static update.rpd...

  • Page 90: Commands And Responses

    Block Diagram The following figure illustrates the role of the Mailbox Client Intel Agilex in a Intel Agilex design. The Mailbox Client IP enables communication with the SDM to access Quad SPI flash memory and system status including temperature and voltage readings.
  • Page 91 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED LENGTH COMMAND / ERROR CODE The following table describes the fields of the header command. Table 23. Mailbox Client Intel Agilex FPGA IP Command and Response Header Description Header Description Reserved [31:28] Reserved.

  • Page 92: Operation Commands

    In the command header, these bits represent command code. In the response header, these bits represent error code. 5.3.1. Operation Commands Table 24. Mailbox Client Intel Agilex FPGA IP Command List and Descriptions (RSU Functions for Non-HPS Variants) Command Code Command...
  • Page 93 When there are no failing images, the following words do not contain meaningful data. State Failure code of the last failing image. The error field has two parts: continued... (10) This number does not include the command and response header. Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 94 If the SDM is in the process of configuring the device or AS x4 is in use, the SDM returns the error response. continued... (10) This number does not include the command and response header. Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 95 The number of words to erase. The erasure size must be a multiple of 4000 (hexadecimal) words. A successful erase returns an OK response code. continued... (10) This number does not include the command and response header. Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 96: Error Code Responses

    The opcode to send the attached flash memory. A successful command returns an OK response code. 5.3.2. Error Code Responses Table 25. Mailbox Client Intel Agilex FPGA IP Error Code Responses and Description Value (Hex) Error Code Response Description Indicates that the command completed successfully.

  • Page 97: Remote System Update Flash Device Layout

    Application image 2 APP_IMAGE2 Varies Varies Application image N APP_IMAGEN (11) The Intel Quartus Prime software reserves an extra 256 KB of memory following this image for potential factory image updates. Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 98: Configuration Firmware Pointer Block (Cpb)

    The configuration firmware accesses the configuration firmware pointer block when performing remote system update. The Intel Quartus Prime Programming Files Generator sets up the initial configuration firmware pointer block. Each copy of the configuration firmware pointer block (CPB0/CPB1) must be exactly 4 KB.

  • Page 99: Intel Agilex Debugging Guide

    Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.

  • Page 100: Intel Agilex Configuration Architecture Overview

    25, 100, or 125 MHz? OSC_CLK_1 For Intel Agilex SX parts ensure that the HPS and EMIF IOPLL are stable and free running before configuration begins. The actual frequency should match the setting specified in Platform Designer.

  • Page 101: Configuration Pin Differences From Previous Device Families

    UG-20205 | 2019.04.03 6.3. Configuration Pin Differences from Previous Device Families Intel Agilex configuration pin behavior is different from earlier device families. Knowing about these differences and how these pins behave can help you understand and debug configuration issues. Configuration Pin Names (Pre-Intel...
  • Page 102 , this pin functions as per the configuration mode selected. Do MSEL[2] SDM_IO9 MSEL[2] MSEL not connect directly to power. Use 4.7 KΩ pull-up or pull-downs, as appropriate. No longer Open Drain. Intel recommends a 10 KΩ pull-up to V NSTATUS nSTATUS CCIO_SDM Not Available Multi-device configuration is not supported.

  • Page 103: Configuration File Format Differences

    The firmware section is not part of the file. The Intel Quartus Prime Pro Edition Programmer adds the firmware to .sof . The programmer adds the firmware when configuring an Intel Agilex device or when it converts the .sof .sof another format.

  • Page 104: Understanding Seus

    6.6. Reading the Unique 64-Bit CHIP ID The Chip ID Intel IP core in each Intel Agilex device stores a unique 64-bit chip ID. After the Chip ID Intel IP core receives a valid clock input, the chip ID is available on the output port.

  • Page 105: Nconfig

    Internal Oscillator option in the Intel Quartus Prime. OSC_CLK_1 • Try configuring the Intel Agilex device with a simple design that does not contain any IP. If configuration via a non-JTAG scheme fails with a simple design, try JTAG configuration with the pins set specifically to JTAG.

  • Page 106: Nstatus

    The pulse ranges from .5 ms to 1.5 ms. assertion is asynchronous to data error detection. Intel Agilex devices do not support the auto-restart nSTATUS configuration after error option.

  • Page 107: Conf_Done And Init_Done

    , weak internal pull-downs pull these pins low at power-on reset. Ensure you specify INIT_DONE SDM_IO16 SDM_IO0 these pins in the Intel Quartus Prime Software or in the Intel Quartus Prime settings file, ( .qsf CONF_DONE are low prior to and during configuration.

  • Page 108: Document Revision History For The Intel Agilex Configuration User Guide

    Initial Release Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.

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