Intel 8XC196K Series User Manual page 388

Symbol
The 87C196CA, 8XC196J x , K x Meets These Specifications (Continued)
T CLKOUT Low to ALE/ADV# Low (8XC196KS, KT, modes 1 and 2 only)
CLLL
Time between CLKOUT going low and ALE/ADV# going low. Use to derive other timings.
T CLKOUT Low to WR# Low
CLWL
Time between CLKOUT going low and WR# being asserted.
T ALE Cycle Time
LHLH
Minimum time between ALE pulses.
T ALE/ADV# High Period
LHLL
Use this specification when designing the external latch.
T Address Hold after ALE/ADV# Low
LLAX
Length of time address is valid after ALE/ADV# falls. Use this specification when designing the
external latch.
T ALE/ADV# Falling to CLKOUT Rising
LLCH
Use to derive other timings.
T ALE/ADV# Low to RD# Low
LLRL
Length of time after ALE/ADV# falls before RD# is asserted. Could be needed to ensure proper
memory decoding takes place before a device is enabled.
T ALE/ADV# Low to WR# Low
LLWL
Length of time after ALE/ADV# falls before WR# is asserted. Could be needed to ensure
proper memory decoding takes place before a device is enabled.
T Data Valid to WR# High
QVWH
Time between data being valid on the bus and WR# going inactive. Memory devices must meet
this specification.
T AD15:8 Hold after RD# High
RHAX
Minimum time the high byte of the address in 8-bit mode will be valid after RD# inactive.
† ††
T BHE# , INST
RHBX
Minimum time these signals will be valid after RD# inactive.
T RD# High to ALE/ADV# Asserted
RHLH
Time between RD# going inactive and the next ALE/ADV#. Useful in calculating time between
inactive and next address valid.
T RD# Low to Address Float
RLAZ
Used to calculate when the 87C196CA, 8XC196J x , K x stops driving address on the bus.
T RD# Low to CLKOUT Low
RLCL
Length of time from RD# asserted to CLKOUT falling edge.
T RD# Low to RD# High
RLRH
RD# pulse width.
†
8XC196K x only; the BUSWIDTH and BHE# pins are not implemented on the 87C196CA, 8XC196J x .
†† 8XC196K x , 87C196CA only; the READY and INST pins are not implemented on the 8XC196J x .
Table 15-8. AC Timing Definitions (Continued)
Hold after RD# High
INTERFACING WITH EXTERNAL MEMORY
Definition
15-39