Intel 8XC196K Series User Manual page 386

Table of Contents

Each symbol consists of two pairs of letters prefixed by "T" (for time). The characters in a pair

indicate a signal and its condition, respectively. Symbols represent the time between the two sig-

nal/condition points. For example,

(Low) and signal D (Input Data) condition V (Valid). Table 15-7 defines the signal and condition

Table 15-8 defines the AC timing specifications that the memory system must meet and those that

the device will provide.

The External Memory System Must Meet These Specifications

Address Valid to Input Data Valid

Maximum time the memory device has to output valid data after the 87C196CA, 8XC196J x , K x

outputs a valid address.

Address Valid to BUSWIDTH

Maximum time after address is valid until BUSWIDTH must be valid. If this specification is

exceeded, the 8XC196K x may not respond with the specified bus cycle.

Address Valid to READY

Maximum time the memory system has to assert READY after the 87C196CA, 8XC196K x

outputs the address to guarantee that at least one wait state will occur.

CLKOUT Low to Input Data Valid

Maximum time the memory system has to output valid data after CLKOUT falls.

Minimum time BUSWIDTH must be held valid after CLKOUT falls. Always 0 ns on the

Hold after CLKOUT Low

Minimum hold time is always 0 ns. If maximum specification is exceeded, additional wait states

8XC196K x only; the BUSWIDTH and BHE# pins are not implemented on the 87C196CA, 8XC196J x .

8XC196K x , 87C196CA only; the READY and INST pins are not implemented on the 8XC196J x .

is the time between signal C (CLKOUT) condition L

Table 15-7. AC Timing Symbol Definitions

Table 15-8. AC Timing Definitions

Hold after CLKOUT Low

INTERFACING WITH EXTERNAL MEMORY

WR#, WRH#, WRL#

No Longer Valid