Intel 8XC196K Series User Manual page 203

8XC196K x , J x , CA USER'S MANUAL
Slave
Port Pin Port
Signal
P3.7:0 SLP7:0
P5.0 SLPALE
P5.1 SLPCS#
P5.2 SLPWR#
P5.3 SLPRD#
P5.4 SLPINT
Table 9-2. Slave Port Control and Status Registers
Mnemonic Address
INT_MASK
INT_MASK1
INT_PEND
9-4
Table 9-1. Slave Port Signals
Slave Port
Signal Type
I/O Slave Port Address/Data bus
Slave port address/data bus in multiplexed mode and slave port
data bus in demultiplexed mode. In multiplexed mode, SLP1 is
the source of the internal control signal, SLP_ADDR.
I Slave Port Address Latch Enable
Functions as either a latch enable input to latch the value on
SLP1 (with a multiplexed address/data bus) or as the source of
the internal control signal, SLP_ADDR (with a demultiplexed
address/data bus).
I Slave Port Chip Select
SLPCS# must be held low to enable slave port operation.
I Slave Port Write Control Input
This active-low signal is an input to the slave. The rising edge of
SLPWR# latches data on port 3 into the P3_PIN or SLP_CMD
register.
SLPWR# is multiplexed with P5.2, WR#, and WRL#.
I Slave Port Read Control Input
This active-low signal is an input to the slave. Data from the
P3_REG or SLP_STAT register is valid after the falling edge of
SLPRD#.
O Slave Port Interrupt
This active-high slave port output signal can be used to interrupt
the master processor.
NOTE: SLPINT is multiplexed with P5.4 and the ONCE# func-
08H Interrupt Mask
Setting bit 6 enables the output buffer empty (OBE) interrupt; clearing
the bit disables it.
Setting bit 7 enables the input buffer full (IBF) interrupt; clearing the bit
disables it.
13H Interrupt Mask 1
Setting bit 0 enables the command buffer full (CBF) interrupt; clearing
the bit disables it.
09H Interrupt Pending
Bit 6, when set, indicates a pending output buffer empty (OBE) interrupt.
This bit is set after the master writes to the data input register, P3_PIN.
Bit 7, when set, indicates a pending input buffer full (IBF). This bit is set
after the master reads from the data output register, P3_REG.
Description
tion (KR, KQ) or a special test-mode-entry pin (KS, KT).
Because driving this pin low on the rising edge of
RESET# could cause the device to enter a reserved
test mode, this pin should not be used as an input.
Description