Operating In Capture Mode - Intel 8XC196K Series User Manual

10.4.1 Operating in Capture Mode

In capture mode, when a valid event occurs on the pin, the value of the selected timer is captured
into a buffer. The timer value is then transferred from the buffer to the EPAx_TIME register,
which sets the EPA interrupt pending bit as shown in Figure 10-6. If enabled, an interrupt is gen-
erated. If a second event occurs before the CPU reads the first timer value in EPAx_TIME, the
current timer value is loaded into the buffer and held there. After the CPU reads the EPAx_TIME
register, the contents of the capture buffer are automatically transferred into EPAx_TIME and the
EPA interrupt pending bit is set.
Pending Bit
Figure 10-6. EPA Simplified Input-Capture Structure
If a third event occurs before the CPU reads the event-time register, the overwrite bit
(EPAx_CON.0) determines how the EPA will handle the event. If the bit is clear, the EPA ignores
the third event. If the bit is set, the third event time overwrites the second event time in the capture
buffer. Both situations set the overrun interrupt pending bit and, if enabled, generate an overrun
interrupt. Table 10-5 summarizes the possible actions when a valid event occurs.
In order for an event to be captured, the signal must be stable for at least two
state times both before and after the transition occurs (Figure 10-7).
TIMER x
Capture Buffer
EPA
Interrupt
Set
EPA x _TIME
Read-out Time Value
NOTE
EVENT PROCESSOR ARRAY (EPA)
Event Occurs
at EPA Pin
A2458-02
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