Table of Contents
Advertisement
PIC
prioritized interrupt
program memory
protected instruction
PSW
PTS
PTSCB
PTS control block
PTS cycle
PTS interrupt
PTS mode
Programmable interrupt controller. The module
responsible for handling interrupts that are to be
serviced by interrupt service routines that you
provide. Also called simply the interrupt controller.
Any maskable interrupt or nonmaskable NMI. Two of
the nonmaskable interrupts (unimplemented opcode
and software trap) are not prioritized; they vector
directly to the interrupt service routine when
executed.
A partition of memory where instructions can be
stored for fetching and execution.
An instruction that prevents an interrupt from being
acknowledged until after the next instruction
executes. The protected instructions are DI, EI, DPTS,
EPTS, POPA, POPF, PUSHA, and PUSHF.
Program status word. The high byte of the PSW is the
status byte, which contains one bit that globally
enables or disables servicing of all maskable
interrupts, one bit that enables or disables the PTS,
and six Boolean flags that reflect the state of the
user's program. The low byte of the PSW is the
INT_MASK register. A push or pop instruction saves
or restores both bytes (PSW + INT_MASK).
Peripheral
transaction server.
hardware interrupt processor.
See PTS control block.
A block of data required for each PTS interrupt. The
microcode executes the proper PTS routine based on
the contents of the PTS control block.
The microcoded response to a single PTS interrupt
request.
Any maskable interrupt that is assigned to the PTS for
interrupt processing.
A microcoded response that enables the PTS to
complete a specific task quickly. These tasks include
transferring a single byte or word, transferring a block
of bytes or words, managing multiple A/D conver-
sions, and generating PWM outputs.
GLOSSARY
The
microcoded
Glossary-7
Advertisement
Table of Contents
