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8XC196K x , J x , CA USER'S MANUAL
6.3
BIDIRECTIONAL PORTS 1, 2, 5, AND 6
Although the bidirectional ports are very similar in both circuitry and configuration, port 5 differs
from the others in some ways. Port 5, a memory-mapped port, uses a standard CMOS input buffer
because of the high speeds required for system control functions. The remaining bidirectional
ports use Schmitt-triggered input buffers for improved noise immunity.
Ports 3 and 4 are significantly different from the other bidirectional ports. See
"Bidirectional Ports 3 and 4 (Address/Data Bus)" on page 6-15 for details on
the structure and operation of these ports.
Table 6-4 lists the bidirectional port pins with their special-function signals and associated periph-
erals.
Port Pin
P1.0
P1.1
P1.2
P1.3
†
P1.4
†
P1.5
†
P1.6
†
P1.7
P2.0
P2.1
P2.2
†
P2.3
P2.4
†
P2.5
P2.6
P2.7
P5.0
†
This pin is not implemented on 8XC196J x and 87C196CA devices.
††
This pin is not implemented on 8XC196J x devices.
†††
P5.4/SLPINT is not implemented on 8XC196J x devices. P5.4 is
implemented on the 87C196CA as a low-speed input/output pin (but it is not
multiplexed with SLPINT).
6-4
NOTE
Table 6-4. Bidirectional Port Pins
Special-function
Special-function
Signal(s)
Signal Type
EPA0
T2CLK
EPA1
EPA2
T2DIR
EPA3
EPA4
EPA5
EPA6
EPA7
TXD
RXD
EXTINT
BREQ#
INTOUT#
HOLD#
HLDA#
CLKOUT
ALE/ADV#
SLPALE
Associated
Peripheral
I/O
EPA
I
Timer 2
I/O
EPA
I/O
EPA
I
Timer 2
I/O
EPA
I/O
EPA
I/O
EPA
I/O
EPA
I/O
EPA
O
SIO
I/O
SIO
I
Interrupts
O
Bus controller
O
Interrupts
I
Bus controller
O
Bus controller
O
Clock generator
O
Bus controller
I
Slave port
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