Design Considerations - Intel 8XC196K Series User Manual

8XC196K x , J x , CA USER'S MANUAL

15.7.5 Design Considerations

In all bus timing modes, for 16-bit bus-width operation, latch the upper and lower address/data
lines. In modes 1 and 2, for 8-bit bus-width operation, also latch the upper and lower address/data
lines; the upper address lines are not driven throughout the entire bus cycle (see Figures 15-22
and 15-23). In modes 0 and 3, for 8-bit bus-width operation, latch only the lower address/data
lines. In these modes, it is not necessary to latch the upper address lines because these lines are
driven throughout the entire bus cycle.
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