Intel 8XC196K Series User Manual page 117

8XC196K x , J x , CA USER'S MANUAL
PTS Single Transfer Mode Control Block
In single transfer mode, the PTS control block contains a source and destination address (PTSSRC
and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT).
7
Unused
7
Unused
15
PTSDST (HI)
7
PTSDST (LO)
15
PTSSRC (HI)
7
PTSSRC (LO)
7
PTSCON M2
7
PTSCOUNT
Register Location
PTSDST PTSCB + 4
PTSSRC PTSCB + 2
Figure 5-12. PTS Control Block – Single Transfer Mode
5-22
0 0 0
0 0 0
PTS Destination Address (high byte)
PTS Destination Address (low byte)
PTS Source Address (high byte)
PTS Source Address (low byte)
M1 M0
Consecutive Byte or Word Transfers
PTS Destination Address
Write the destination memory location to this register. A valid address is
any unreserved memory location; however, it must point to an even
address if word transfers are selected.
PTS Source Address
Write the source memory location to this register. A valid address is any
unreserved memory location; however, it must point to an even address
if word transfers are selected.
0 0 0
0 0 0
BW SU DU
Function
0
0 0
0
0 0
8
0
8
0
0
SI DI
0