Intel 8XC196K Series User Manual page 514

Name Type
††
NMI I
ONCE# I
P0.7:0 (K x ) I
P0.7:2 (Jx, CA)
P1.7:0 (K x )
I/O
P1.3:0 (Jx,
CA)
†
This signal is not implemented on the 8XC196J x or 87C196CA (see "Design Considerations for
8XC196JQ, JR, JT, and JV Devices" on page 2-14 or "Design Considerations for 87C196CA Devices" on
page 2-13).
††
This signal is not implemented on the 8XC196J x (see "Design Considerations for 8XC196JQ, JR, JT, and
JV Devices" on page 2-14).
Table B-6. Signal Descriptions (Continued)
Nonmaskable Interrupt
In normal operating mode, a rising edge on NMI causes a vector through the
NMI interrupt at location 203EH. NMI must be asserted for greater than one
state time to guarantee that it is recognized.
In idle mode, a rising edge on the NMI pin causes the device to return to normal
operation, where the first action is to execute the NMI service routine. After
completion of the service routine, execution resumes at the instruction following
the IDLPD instruction that put the device into idle mode.
In powerdown mode, a rising edge on the NMI pin does not cause the device to
exit powerdown.
On-circuit Emulation
Holding ONCE# low during the rising edge of RESET# places the device into
on-circuit emulation (ONCE) mode. This mode puts all pins into a high-
impedance state, thereby isolating the device from other components in the
system. The value of ONCE# is latched when the RESET# pin goes inactive.
While the device is in ONCE mode, you can debug the system using a clip-on
emulator. To exit ONCE mode, reset the device by pulling the RESET# signal
low. To prevent inadvertent entry into ONCE mode, either configure this pin as
an output or hold it high during reset and ensure that your system meets the V
specification (see datasheet).
On the 8XC196KR and KQ, ONCE# is multiplexed with P5.4 and SLPINT.
On the 8XC196KT and KS, ONCE# is multiplexed with P2.6 and HLDA#.
On the 8XC196J x and CA, ONCE# is multiplexed with P2.6.
Port 0
This is a high-impedance, input-only port. Port 0 pins should not be left floating.
These pins may individually be used as analog inputs (ACH x ) or digital inputs
(P0. x ). While it is possible for the pins to function simultaneously as analog and
digital inputs, this is not recommended because reading port 0 while a
conversion is in process can produce unreliable conversion results.
ANGND and V must be connected for port 0 to function.
REF
On the 8XC196K x, P0.3:0 are multiplexed with ACH3:0 and P0.7:4 are
multiplexed with ACH7:4 and PMODE.3:0.
On the 8XC196J x and 87C196CA, P0.3:2 are multiplexed with ACH3:2 and
P0.7:4 are multiplexed with ACH7:4 and PMODE.3:0.
P0.1:0 are not implemented on the 8XC196J x and 87C196CA.
Port 1
This is a standard, bidirectional port that is multiplexed with individually
selectable special-function signals.
Port 1 is multiplexed as follows: P1.0/EPA0/T2CLK, P1.1/EPA1,
P1.2/EPA2/T2DIR, P1.3/EPA3, P1.4/EPA4, P1.5/EPA5, P1.6/EPA6, and
P1.7/EPA7.
P1.7:4 are not implemented on the 8XC196J x and 87C196CA.
SIGNAL DESCRIPTIONS
Description
IH
B-13