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8XC196KQ,

8XC196KR,

8XC196KS,

8XC196KT,

8XC196JQ,

8XC196JR,

8XC196JT,

8XC196JV,

87C196CA

8XC196Kx, 8XC196Jx,

87C196CA

Microcontroller Family

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Page 1 8XC196Kx, 8XC196Jx, 87C196CA Microcontroller Family User’s Manual Includes 8XC196KQ, 8XC196KR, 8XC196KS, 8XC196KT, 8XC196JQ, 8XC196JR, 8XC196JT, 8XC196JV, 87C196CA...
Page 2 8XC196Kx, 8XC196Jx, 87C196CA Microcontroller Family User’s Manual Includes 8XC196KQ, 8XC196KR, 8XC196KS, 8XC196KT, 8XC196JQ, 8XC196JR, 8XC196JT, 8XC196JV, 87C196CA June 1995 Order Number 272258-002...
Page 3 Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.
Page 4: Table Of Contents
CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL MANUAL CONTENTS ....................1-1 NOTATIONAL CONVENTIONS AND TERMINOLOGY ..........1-3 RELATED DOCUMENTS ....................1-5 ELECTRONIC SUPPORT SYSTEMS ................1-8 1.4.1 FaxBack Service .......................1-8 1.4.2 Bulletin Board System (BBS) ..................1-9 ® 1.4.2.1 How to Find MCS 96 Microcontroller Files on the BBS ........1-9 1.4.2.2 How to Find Ap BUILDER Software and Hypertext Documents on the BBS ..1-10...
Page 5 CONTENTS 2.6.2 Testing the Printed Circuit Board ................2-12 2.6.3 Programming the Nonvolatile Memory ..............2-12 DESIGN CONSIDERATIONS FOR 87C196CA DEVICES.......... 2-13 DESIGN CONSIDERATIONS FOR 8XC196JQ, JR, JT, AND JV DEVICES....2-14 CHAPTER 3 PROGRAMMING CONSIDERATIONS OVERVIEW OF THE INSTRUCTION SET..............3-1 3.1.1 BIT Operands ......................3-2 3.1.2...
Page 6 CONTENTS 4.1.4.1 Reserved Memory Locations ................4-4 4.1.4.2 Interrupt and PTS Vectors ..................4-4 4.1.4.3 Security Key ......................4-4 4.1.4.4 Chip Configuration Bytes (CCBs) .................4-4 4.1.5 Special-function Registers (SFRs) ................4-5 4.1.5.1 Memory-mapped SFRs ..................4-5 4.1.5.2 Peripheral SFRs ....................4-6 4.1.6 Internal RAM (Code RAM) ..................4-10 4.1.7 Register File ......................4-10 4.1.7.1...
Page 7 CONTENTS 5.6.1 Specifying the PTS Count ..................5-19 5.6.2 Selecting the PTS Mode ..................5-21 5.6.3 Single Transfer Mode ....................5-21 5.6.4 Block Transfer Mode ....................5-24 5.6.5 A/D Scan Mode .......................5-26 5.6.5.1 A/D Scan Mode Cycles ..................5-29 5.6.5.2 A/D Scan Mode Example 1 ................5-29 5.6.5.3 A/D Scan Mode Example 2 ................5-30 5.6.6...
Page 8 CONTENTS 7.4.3 Programming the Baud Rate and Clock Source .............7-10 7.4.4 Enabling the Serial Port Interrupts ................7-12 7.4.5 Determining Serial Port Status ................7-13 PROGRAMMING EXAMPLE USING AN INTERRUPT-DRIVEN ROUTINE ....7-14 CHAPTER 8 SYNCHRONOUS SERIAL I/O (SSIO) PORT SYNCHRONOUS SERIAL I/O (SSIO) PORT FUNCTIONAL OVERVIEW....8-1 SSIO PORT SIGNALS AND REGISTERS ..............
Page 9 CONTENTS CHAPTER 10 EVENT PROCESSOR ARRAY (EPA) 10.1 EPA FUNCTIONAL OVERVIEW ................. 10-1 10.2 EPA AND TIMER/COUNTER SIGNALS AND REGISTERS ........10-2 10.3 TIMER/COUNTER FUNCTIONAL OVERVIEW............10-6 10.3.1 Cascade Mode (Timer 2 Only) ................10-7 10.3.2 Quadrature Clocking Mode ..................10-7 10.4 EPA CHANNEL FUNCTIONAL OVERVIEW ...............
Page 10 CONTENTS 11.6.1.1 Minimizing the Effect of High Input Source Resistance ........11-12 11.6.1.2 Suggested A/D Input Circuit ................11-13 11.6.1.3 Analog Ground and Reference Voltages ............11-13 11.6.1.4 Using Mixed Analog and Digital Inputs ............11-14 11.6.2 Understanding A/D Conversion Errors ..............11-14 CHAPTER 12 CAN SERIAL COMMUNICATIONS CONTROLLER 12.1 CAN FUNCTIONAL OVERVIEW .................
Page 11 CONTENTS 13.2 APPLYING AND REMOVING POWER ............... 13-4 13.3 NOISE PROTECTION TIPS ..................13-4 13.4 PROVIDING THE CLOCK ................... 13-5 13.4.1 Using the On-chip Oscillator ...................13-5 13.4.2 Using a Ceramic Resonator Instead of a Crystal Oscillator ........13-7 13.4.3 Providing an External Clock Source ................13-7 13.5 RESETTING THE DEVICE..................
Page 12 CONTENTS Regaining Bus Control (8XC196K x Only) .............15-20 15.5.4 15.6 BUS-CONTROL MODES................... 15-20 15.6.1 Standard Bus-control Mode ..................15-20 15.6.2 Write Strobe Mode ....................15-24 15.6.3 Address Valid Strobe Mode ..................15-26 15.6.4 Address Valid with Write Strobe Mode ..............15-29 15.7 BUS TIMING MODES (8XC196KS, KT ONLY) ............15-30 15.7.1 Mode 3, Standard Mode ..................15-32 15.7.2...
Page 13 CONTENTS 16.9.5 ROM-dump Mode ....................16-31 16.10 SERIAL PORT PROGRAMMING MODE ..............16-32 16.10.1 Serial Port Programming Circuit and Memory Map ..........16-32 16.10.2 Changing Serial Port Programming Defaults ............16-34 16.10.3 Executing Programs from Internal RAM ..............16-35 16.10.4 Reduced Instruction Set Monitor (RISM) ..............16-35 16.10.5 RISM Command Descriptions ................16-36 16.10.6 RISM Command Examples ...................16-38 16.10.6.1 Example 1 —...
Page 14 CONTENTS FIGURES Figure Page 8XC196K x Block Diagram ....................2-3 Block Diagram of the Core ...................2-3 Clock Circuitry ......................2-7 Internal Clock Phases ....................2-8 Register File Memory Map ..................4-11 Windowing ........................4-14 Window Selection Register (WSR)................4-15 Flow Diagram for PTS and Standard Interrupts ............5-2 Standard Interrupt Response Time ................5-9 PTS Interrupt Response Time ..................5-10 PTS Select (PTSSEL) Register ..................5-12...
Page 15 CONTENTS FIGURES Figure Page DPRAM vs Slave-Port Solution ..................9-2 Slave Port Block Diagram.....................9-3 Master/Slave Hardware Connections ................9-7 Standard Slave Mode Timings (Demultiplexed Bus) ..........9-10 Standard or Shared Memory Mode Timings (Multiplexed Bus)........9-13 Slave Port Control (SLP_CON) Register..............9-15 Slave Port Status (SLP_STAT) Register ..............9-17 10-1 EPA Block Diagram ....................10-2 10-2...
Page 16 CONTENTS FIGURES Figure Page 12-11 CAN Message 15 Mask (CAN_MSK15) Register.............12-20 CAN Message Object x Configuration (CAN_MSGxCFG) Register......12-21 12-12 12-13 CAN Message Object x Identifier (CAN_MSG x ID0–3) Register ......12-22 12-14 CAN Message Object x Control 0 (CAN_MSGxCON0) Register ......12-24 12-15 CAN Message Object x Control 1 (CAN_MSG x CON1) Register ......12-26 12-16...
Page 17 CONTENTS FIGURES Figure Page 15-15 Address Valid Strobe Mode..................15-26 15-16 Comparison of ALE and ADV# Bus Cycles ..............15-26 15-17 8-bit System with Flash ....................15-27 15-18 16-bit System with EPROM ..................15-28 15-19 Timings of Address Valid with Write Strobe Mode ...........15-29 15-20 16-bit System with RAM ...................15-30 15-21...
Page 18 CONTENTS TABLES Table Page Handbooks and Product Information ................1-6 Application Notes, Application Briefs, and Article Reprints ..........1-6 ® 96 Microcontroller Datasheets (Commercial/Express) ........1-7 ® 96 Microcontroller Datasheets (Automotive) .............1-7 ® 96 Microcontroller Quick References ..............1-7 Features of the 8XC196K x , J x , CA Product Family............2-2 State Times at Various Frequencies ................2-8 Unsupported Functions in 87C196CA Devices ............2-13 Unsupported Functions in 8XC196J x Devices ............2-14...
Page 19 CONTENTS TABLES Table Page Logic Table for Bidirectional Ports in Special-function Mode ........6-9 Control Register Values for Each Configuration............6-11 Port Configuration Example ..................6-11 6-10 Port Pin States After Reset and After Example Code Execution........6-12 6-11 Ports 3 and 4 Pins ......................6-16 6-12 Ports 3 and 4 Control and Status Registers ...............6-16 6-13...
Page 20 CONTENTS TABLES Table Page 14-4 Test-mode-entry Pins ....................14-10 15-1 External Memory Interface Signals................15-1 15-2 READY Signal Timing Definitions................15-16 15-3 HOLD#, HLDA# Timing Definitions ................15-18 15-4 Maximum Hold Latency ....................15-19 15-5 Bus-control Mode .....................15-20 15-6 Modes 0, 1, 2, and 3 Timing Comparisons...............15-32 15-7 AC Timing Symbol Definitions ..................15-37 15-8...
Page 21 CONTENTS TABLES Table Page Modules and Related Registers .................. C-1 Register Name, Address, and Reset Status..............C-2 CAN_EGMSK Addresses and Reset Values............. C-15 CAN_MSG x CFG Addresses and Reset Values ............C-17 CAN_MSG x CON0 Addresses and Reset Values............C-19 CAN_MSG x CON1 Addresses and Reset Values............
Page 22: Guide To This Manual
Guide to This Manual...
Page 24: Manual Contents
CHAPTER 1 GUIDE TO THIS MANUAL This manual describes the 8XC196Kx, Jx, CA family of embedded microcontrollers. It is intend- ed for use by both software and hardware designers familiar with the principles of microcontrol- lers. This chapter describes what you’ll find in this manual, lists other documents that may be useful, and explains how to access the support services we provide to help you complete your de- sign.
Page 25 CAN controller and explains how to configure it. This integrated peripheral is similar to Intel’s standalone 82527 CAN serial communications controller, supporting both the standard and extended message frames specified by the CAN 2.0 protocol parts A and B.
Page 26: Notational Conventions And Terminology
GUIDE TO THIS MANUAL Appendix C — Registers — provides a compilation of all device registers arranged alphabeti- cally by register mnemonic. It also includes tables that list the windowed direct addresses for all SFRs in each possible window. Glossary — defines terms with special meaning used throughout this manual. Index —...
Page 27 8XC196K x , J x , CA USER’S MANUAL Numbers Hexadecimal numbers are represented by a string of hexadecimal digits followed by the character H. Decimal and binary numbers are represented by their customary notations. (That is, 255 is a decimal number and 1111 1111 is a binary number.
Page 28: Related Documents
For a complete list of available printed documents, please or- der the literature catalog (order number 210621). To order documents, please call the Intel literature center for your area (telephone numbers are listed on page 1-11).
Page 29 Complete set of Intel handbooks on CD-ROM. Handbook Set — handbooks and product overview 231003 Complete set of Intel’s product line handbooks. Contains datasheets, application notes, article reprints and other design information on microprocessors, periph- erals, embedded controllers, memory components, single-board computers, microcommunications, software development tools, and operating systems.
Page 30 AP-477, Low Voltage Embedded Design †† 272324 AP-483, Application Examples Using the 8XC196MC/MD Microcontroller 272282 † AP-700, Intel Fuzzy Logic Tool Simplifies ABS Design 272595 AP-711, EMI Design Techniques for Microcontrollers in Automotive Applications 272324 ® AP-715, Interfacing an I...
Page 31: Electronic Support Systems
8XC196K x , J x , CA USER’S MANUAL ELECTRONIC SUPPORT SYSTEMS Intel’s FaxBack* service and application BBS provide up-to-date technical information. We also maintain several forums on CompuServe and offer a variety of information on the World Wide Web. These systems are available 24 hours a day, 7 days a week, providing technical information whenever you need it.
Page 32: Bulletin Board System (Bbs)
Application notes, utilities, and product literature are available from the BBS. To access the files, complete these steps: Enter F from the BBS Main menu. The BBS displays the Intel Apps Files menu. Type L and press <Enter>. The BBS displays the list of areas and prompts for the area number.
Page 33: How To Find Ap Builder Software And Hypertext Documents On The Bbs
BBS. To access the files, complete these steps: Type F from the BBS Main menu. The BBS displays the Intel Apps Files menu. Type L and press <Enter>. The BBS displays the list of areas and prompts for the area number.
Page 34: Technical Support
Europe (U.K.) 44(0)1793-421333 Germany 44(0)1793-421777 France 81(0)120-47-88-32 Japan (fax only) TRAINING CLASSES In the U.S. and Canada, you can register for training classes through the Intel customer training center. Classes are held in the U.S. 1-800-234-8806 U.S. and Canada 1-11...
Page 36: Architectural Overview
Architectural Overview...
Page 38: Typical Applications
CHAPTER 2 ARCHITECTURAL OVERVIEW The 16-bit 8XC196Kx, 8XC196Jx, and 87C196CA CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output (I/O) operations. They share a common ar- ® chitecture and instruction set with other members of the MCS 96 microcontroller family. This chapter provides a high-level overview of the architecture.
Page 39: Device Features
8XC196K x , J x , CA USER’S MANUAL DEVICE FEATURES Table 2-1 lists the features of each member of the 8XC196Kx family. Table 2-1. Features of the 8XC196K x, J x , CA Product Family OTPROM/ SIO/ External Register Code/ Device Pins...
Page 40 ARCHITECTURAL OVERVIEW Optional Interrupt Core Controller Clock and Code/Data Power Mgmt. Slave SSIO Port Note: The slave port is unique to 8XC196K x devices. The CAN peripheral is unique to the 8XC196CA. A2799-02 Figure 2-1. 8XC196K x Block Diagram Memory Controller Register File RALU Prefetch Queue...
Page 41: Cpu Control
8XC196K x , J x , CA USER’S MANUAL 2.3.1 CPU Control The CPU is controlled by the microcode engine, which instructs the RALU to perform operations using bytes, words, or double words from either the 256-byte lower register file or through a win- dow that directly accesses the upper register file.
Page 42: Code Execution
ARCHITECTURAL OVERVIEW The RALU uses the upper- and lower-word registers together for the 32-bit instructions and as temporary registers for many instructions. These registers have their own shift logic and are used for operations that require logical shifts, including normalize, multiply, and divide operations. The six-bit loop counter counts repetitive shifts.
Page 43: Memory Controller
8XC196K x , J x , CA USER’S MANUAL 2.3.4 Memory Controller The RALU communicates with all memory, except the register file and peripheral SFRs, through the memory controller. (It communicates with the upper register file through the memory control- ler except when windowing is used;...
Page 44: Internal Timing
ARCHITECTURAL OVERVIEW INTERNAL TIMING The clock circuitry (Figure 2-3) receives an input clock signal on XTAL1 provided by an external crystal or oscillator and divides the frequency by two. The clock generators accept the divided input frequency from the divide-by-two circuit and produce two nonoverlapping internal timing signals, PH1 and PH2.
Page 45: Internal Peripherals
8XC196K x , J x , CA USER’S MANUAL XTAL1 1 State Time 1 State Time CLKOUT Phase 1 Phase 2 Phase 1 Phase 2 A0114-02 Figure 2-4. Internal Clock Phases The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state.
Page 46: I/O Ports
ARCHITECTURAL OVERVIEW 2.5.1 I/O Ports The 8XC196Kx, 8XC196Jx, and 87C196CA have seven I/O ports, ports 0–6. Individual port pins are multiplexed to serve as standard I/O or to carry special-function signals associated with an on-chip peripheral or an off-chip component. If a particular special-function signal is not used in an application, the associated pin can be individually configured to serve as a standard I/O pin.
Page 47: Slave Port (8Xc196K X Only)
8XC196K x , J x , CA USER’S MANUAL Slave Port (8XC196K x Only) 2.5.4 The slave port offers an alternative for communication between two CPU devices. Traditionally, system designers have had three alternatives for achieving this communication — a serial link, a parallel bus without a dual-port RAM (DPRAM), or a parallel bus with a DPRAM to hold shared data.
Page 48: Analog-To-Digital Converter
The 87C196CA device has a peripheral not found on 8XC196Jx or 8XC196Kx devices, the CAN (controller area network) peripheral. The CAN serial communications controller manages com- munications between multiple network nodes. This integrated peripheral is similar to Intel’s standalone 82527 CAN serial communications controller, supporting both the standard and ex- tended message frames specified by the CAN 2.0 protocol parts A and B.
Page 49: Reducing Power Consumption
• Slave programming allows a master EPROM programmer to program and verify one or more slave MCS 96 microcontrollers. Programming vendors and Intel distributors typically use this mode to program a large number of microcontrollers with a customer’s code and data.
Page 50: Design Considerations For 87C196Ca Devices
ARCHITECTURAL OVERVIEW Chapter 16, “Programming the Nonvolatile Memory,” provides recommended circuits, the corre- sponding memory maps, and flow diagrams. It also provides procedures for auto programming and describes the commands used for serial port programming. DESIGN CONSIDERATIONS FOR 87C196CA DEVICES Some functions that were implemented on 8XC196Kx devices are omitted from the 87C196CA.
Page 51: Design Considerations For 8Xc196Jq, Jr, Jt, And Jv Devices
8XC196K x , J x , CA USER’S MANUAL DESIGN CONSIDERATIONS FOR 8XC196JQ, JR, JT, AND JV DEVICES The 8XC196Jx devices are 52-lead versions of 8XC196Kx devices. Some functions were re- moved to reduce the pin count (Table 2-4). Table 2-4. Unsupported Functions in 8XC196J x Devices Removed Pins Unsupported Functions P0.0 and P0.1...
Page 52 ARCHITECTURAL OVERVIEW Follow these recommendations to help maintain hardware and software compatibility between 52-lead, 68-lead, and future devices. • Bus width. Since the 8XC196Jx has neither a WRH# nor a BUSWIDTH pin, the device cannot dynamically switch between 8- and 16-bit bus widths. Program the CCBs to select 8- bit bus mode.
Page 54: Programming Considerations
Programming Considerations...
Page 56: Overview Of The Instruction Set
CHAPTER 3 PROGRAMMING CONSIDERATIONS ® This section provides an overview of the instruction set of the MCS 96 microcontrollers and of- fers guidelines for program development. For detailed information about specific instructions, see Appendix A. INSTRUCTION SET OVERVIEW OF THE The instruction set supports a variety of operand types likely to be useful in control applications (see Table 3-1).
Page 57: Bit Operands
8XC196K x , J x , CA USER’S MANUAL Table 3-2 lists the equivalent operand-type names for both C programming and assembly lan- guage. Table 3-2. Equivalent Operand Types for Assembly and C Programming Languages Operand Types Assembly Language Equivalent C Programming Language Equivalent BYTE BYTE...
Page 58: Integer Operands
PROGRAMMING CONSIDERATIONS WORDs must be aligned at even byte boundaries in the address space. The least-significant byte of the WORD is in the even byte address, and the most-significant byte is in the next higher (odd) address. The address of a WORD is that of its least-significant byte (the even byte address). WORD operations to odd addresses are not guaranteed to operate in a consistent manner.
Page 59: Long-Integer Operands
8XC196K x , J x , CA USER’S MANUAL 3.1.7 LONG-INTEGER Operands A LONG-INTEGER is a 32-bit, signed variable that can take on values from –2,147,483,648 (– 2 ) through +2,147,483,647 (+2 –1) . The architecture directly supports LONG-INTEGER operands only as the operand in shift operations, as the dividend in 32-by-16 divide operations, and as the product of 16-by-16 multiply operations.
Page 60: Addressing Modes
PROGRAMMING CONSIDERATIONS ADDRESSING MODES The instruction set uses four basic addressing modes: • direct • immediate • indirect (with or without autoincrement) • indexed (short-, long-, or zero-indexed) The stack pointer can be used with indirect addressing to access the top of the stack, and it can also be used with short-indexed addressing to access data within the stack.
Page 61: Direct Addressing
8XC196K x , J x , CA USER’S MANUAL Table 3-3. Definition of Temporary Registers Temporary Register Description word-aligned 16-bit register; AH is the high byte of AX and AL is the low byte word-aligned 16-bit register; BH is the high byte of BX and BL is the low byte word-aligned 16-bit register;...
Page 62: Indirect Addressing With Autoincrement
PROGRAMMING CONSIDERATIONS ; AL ← BL + MEM_BYTE(CX) ADDB AL,BL,[CX] ; MEM_WORD(AX) ← MEM_WORD(SP) [AX] ; SP ← SP + 2 3.2.3.1 Indirect Addressing with Autoincrement You can choose to automatically increment the indirect address after the current access. You spec- ify autoincrementing by adding a plus sign (+) to the end of the indirect reference.
Page 63: Long-Indexed Addressing
8XC196K x , J x , CA USER’S MANUAL The instruction LD AX,12[BX] loads AX with the contents of the memory location that resides at address BX+12. That is, the instruction adds the constant 12 (the offset) to the contents of BX (the base address), then loads AX with the contents of the resulting address.
Page 64: Assembly Language Addressing Mode Selections
PROGRAMMING CONSIDERATIONS ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS The assembly language simplifies the choice of addressing modes. Use these features wherever possible. 3.3.1 Direct Addressing The assembly language chooses between direct and zero-indexed addressing depending on the memory location of the operand. Simply refer to the operand by its symbolic name. If the operand is in the lower register file, the assembly language chooses a direct reference.
Page 65: Addressing 32-Bit Operands
8XC196K x , J x , CA USER’S MANUAL To use these registers effectively, you must have some overall strategy for allocating them. The C programming language adopts a simple, effective strategy. It allocates the eight bytes beginning at address 1CH as temporary storage and treats the remaining area in the register file as a segment of memory that is allocated as required.
Page 66: Software Protection Features And Guidelines
PROGRAMMING CONSIDERATIONS If a procedure returns a value to the calling code (as opposed to modifying more global variables) the result is returned in the temporary storage space (TMPREG0, in this example) starting at 1CH. TMPREG0 is viewed as either an 8-, 16-, or 32-bit variable, depending on the type of the proce- dure.
Page 67 8XC196K x , J x , CA USER’S MANUAL When using the watchdog timer (WDT) for software protection, we recommend that you reset the WDT from only one place in code, reducing the chance of an undesired WDT reset. The section of code that resets the WDT should monitor the other code sections for proper operation.
Page 68: Memory Partitions
Memory Partitions...
Page 70: External Devices (Memory Or I/O)
CHAPTER 4 MEMORY PARTITIONS This chapter describes the address space, its major partitions, and a windowing technique for ac- cessing the upper register file and peripheral SFRs with register-direct instructions. MEMORY PARTITIONS Table 4-1 is a memory map of the 8XC196CA, 8XC196Jx, and 8XC196Kx devices. The remain- der of this section describes the partitions.
Page 71 8XC196K x , J x , CA USER’S MANUAL Table 4-1. Memory Map Device (Note 1) and Hex Address Range Addressing Description Modes FFFF FFFF FFFF FFFF FFFF FFFF External device (memory or I/O) Indirect or A000 6000 6000 8000 A000 E000 connected to address/data bus...
Page 72: Program Memory
MEMORY PARTITIONS 4.1.3 Program Memory Program memory occupies a memory partition beginning at 2080H. (See Table 4-1 for the ending address for each device.) This entire partition is available for storing executable code and data. The EA# signal controls access to program memory. Accesses to this address range are directed to internal memory if EA# is held high and to external memory if EA# is held low.
Page 73: Reserved Memory Locations
8XC196K x , J x , CA USER’S MANUAL 4.1.4.1 Reserved Memory Locations Several memory locations are reserved for testing or for use in future products. Do not read or write these locations except to initialize them. The function or contents of these locations may change in future revisions;...
Page 74: Special-Function Registers (Sfrs)
MEMORY PARTITIONS 4.1.5 Special-function Registers (SFRs) These devices have both memory-mapped SFRs and peripheral SFRs. The memory-mapped SFRs must be accessed using indirect or indexed addressing modes, and they cannot be win- dowed. The peripheral SFRs are physically located in the on-chip peripherals, and they can be windowed (see “Windowing”...
Page 75: Peripheral Sfrs
8XC196K x , J x , CA USER’S MANUAL 4.1.5.2 Peripheral SFRs Locations 1F00–1FDFH provide access to the peripheral SFRs (Table 4-4). Locations in this range that are omitted from the table are reserved. The peripheral SFRs are I/O control registers; they are physically located in the on-chip peripherals.
Page 76 MEMORY PARTITIONS Table 4-4. Peripheral SFRs Ports 0, 1, 2, and 6 SFRs Timer 1, Timer 2, and EPA SFRs Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte Low (Even) Byte † 1FDEH Reserved Reserved 1F9EH TIMER2 (H) TIMER2 (L) 1FDCH Reserved...
Page 77 8XC196K x , J x , CA USER’S MANUAL Table 4-5. CAN Peripheral SFRs — 8XC196CA Only Message 15 Message 11 Addr High (Odd) Byte Low (Even) Byte Addr High (Odd) Byte Low (Even) Byte 1EFEH Reserved CAN_MSG15DATA7 1EBEH Reserved CAN_MSG11DATA7 1EFCH CAN_MSG15DATA6...
Page 78 MEMORY PARTITIONS Table 4-5. CAN Peripheral SFRs — 8XC196CA Only (Continued) Message 7 Message 3 and Bit Timing 0 Addr High (Odd) Byte Low (Even) Byte Addr High (Odd) Byte Low (Even) Byte † 1E7EH Reserved CAN_MSG7DATA7 1E3EH CAN_BTIME0 CAN_MSG3DATA7 1E7CH CAN_MSG7DATA6 CAN_MSG7DATA5...
Page 79: Internal Ram (Code Ram)
8XC196K x , J x , CA USER’S MANUAL 4.1.6 Internal RAM (Code RAM) These devices have up to 512 bytes of internal RAM (see Table 4-1 on page 4-2 for details) be- ginning at location 0400H. Although it is sometimes called code RAM to distinguish it from reg- ister RAM, this internal RAM can store either executable code or data.
Page 80: General-Purpose Register Ram
MEMORY PARTITIONS Address 03FFH (CA, JT, JV, KS, KT) General-purpose Register RAM 01FFH (JR, KR) 017FH (JQ, KQ) Address 0100H 00FFH 03FFH General-purpose Upper Register RAM Register File 0100H 001AH 0019H Stack Pointer 00FFH Lower 0018H 0017H Register File CPU SFRs 0000H 0000H A3073-02...
Page 81 8XC196K x , J x , CA USER’S MANUAL 4.1.7.1 General-purpose Register RAM The lower register file contains general-purpose register RAM. The stack pointer locations can also be used as general-purpose register RAM when stack operations are not being performed. The RALU can access this memory directly, using register-direct addressing.
Page 82: Cpu Special-Function Registers (Sfrs)
MEMORY PARTITIONS The following example initializes the top of the upper register file (8XC196CA, JT, JV, KS, KT) as the stack. (For the 8XC196JR or KR, the immediate value would be #200H; for the 8XC196JQ or KQ, it would be #180H.) SP, #400H ;Load stack pointer The following example shows how to allow the linker locator to determine where the stack fits...
Page 83: Selecting A Window
8XC196K x , J x , CA USER’S MANUAL Windowing maps a segment of higher memory (the upper register file or peripheral SFRs) into the lower register file. The window selection register (WSR) selects a 32-, 64-, or 128-byte seg- ment of higher memory to be windowed into the top of the lower register file space.
Page 84 MEMORY PARTITIONS Table 4-8 on page 4-16 provides a quick reference of WSR values for windowing the peripheral SFRs. Table 4-9 on page 4-16 lists the WSR values for windowing the upper register file. Table 4-9 on page 4-16 lists the WSR values for windowing the additional register RAM of the 8XC196JV.
Page 85 8XC196K x , J x , CA USER’S MANUAL Table 4-8. Selecting a Window of Peripheral SFRs WSR Value for WSR Value for WSR Value for Peripheral 32-byte Window 64-byte Window 128-byte Window (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Ports 0, 1, 2, 6 A/D converter, EPA interrupts EPA compare 0–1, capture/compare 8–9, timers EPA capture/compare 0–7...
Page 86: Addressing A Location Through A Window
MEMORY PARTITIONS Table 4-9. Selecting a Window of the Upper Register File (Continued) WSR Value WSR Value WSR Value Register RAM for 32-byte Window for 64-byte Window for 128-byte Window Locations (00E0–00FFH) (00C0–00FFH) (0080–00FFH) 0160–017FH 0140–015FH 0120–013FH 0100–011FH Table 4-10. Selecting a Window of Upper Register RAM — 8XC196JV Only WSR Value WSR Value WSR Value...
Page 87 8XC196K x , J x , CA USER’S MANUAL Appendix C includes a table of the windowable SFRs with the WSR values and windowed direct addresses for each window size. Examples beginning on page 4-20 explain how to determine the WSR value and windowed direct address for any windowable location.
Page 88 MEMORY PARTITIONS Table 4-11. Windows (Continued) WSR Value for WSR Value WSR Value Base 128-byte for 32-byte Window for 64-byte Window Address Window (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Register RAM (8XC196JV Only; Continued) 1C60H 1C40H 1C20H 1C00H Upper Register File (8XC196CA, JT, JV, KS, KT Only) 03E0H 03C0H 03A0H...
Page 89: 32-Byte Windowing Example
8XC196K x , J x , CA USER’S MANUAL Table 4-12. Windowed Base Addresses WSR Windowed Base Address Window Size (Base Address in Lower Register File) 32-byte 00E0H 64-byte 00C0H 128-byte 0080H Appendix C includes a table of the windowable SFRs with the WSR values and direct addresses for each window size.
Page 90: Unsupported Locations Windowing Example
MEMORY PARTITIONS 4.2.2.4 Unsupported Locations Windowing Example Assume that you wish to access location 1FF1H (the P5_MODE register, a memory-mapped SFR) with register-direct addressing through a 128-byte window. This location is in the range of addresses (1FE0–1FFFH) that cannot be windowed. Although you could set up the window by writing 1FH to the WSR, reading this location through the window would return FFH (all ones) and writing to it would not change the contents.
Page 91 8XC196K x , J x , CA USER’S MANUAL public function2 extrn ?WSR 14h:byte 18h:word oseg var1: var2: var3: cseg function2: push ;Prolog code for wsr wsr, #?WSR ;Prolog code for wsr add var1, var2, var3 wsr, [sp] ;Epilog code for wsr add sp, #2 ;Epilog code for wsr ******************************...
Page 92: Windowing And Addressing Modes
MEMORY PARTITIONS This listing shows the disassembled code: 2080H ;C814 | PUSH 2082H ;B14814 | LDB WSR,#48H 2085H ;44E4E2E0 | ADD E0H,E2H,E4H 2089H ;B21814 | LDB WSR,[SP] 208CH ;65020018 | ADD SP,#02H 2090H | RET 2091H ;C814 | PUSH 2093H ;B14814 | LDB WSR,#48H...
Page 94: Standard And Pts Interrupts
Standard and PTS Interrupts...
Page 96: Overview
CHAPTER 5 STANDARD AND PTS INTERRUPTS This chapter describes the interrupt control circuitry, priority scheme, and timing for standard and peripheral transaction server (PTS) interrupts. It discusses the three special interrupts and the five PTS modes, two of which are used with the EPA to produce pulse-width modulated (PWM) out- puts.
Page 97 8XC196K x , J x , CA USER’S MANUAL Interrupt Pending or PTSSRV Bit Set Pending INT_MASK. x Return = 1? Interrupts Return Enabled? Enabled PTSSEL. x Bit = 1? Priority Encoder Highest Priority Interrupt Priority Encoder Highest Priority PTS Interrupt PTSSRV.
Page 98: Interrupt Signals And Registers
STANDARD AND PTS INTERRUPTS INTERRUPT SIGNALS AND REGISTERS Table 5-1 describes the external interrupt signals and Table 5-2 describes the control and status registers for both the interrupt controller and PTS. Table 5-1. Interrupt Signals PWM Signal Port Pin Type Description EXTINT P2.2...
Page 99: Interrupt Sources And Priorities
8XC196K x , J x , CA USER’S MANUAL Table 5-2. Interrupt and PTS Control and Status Registers (Continued) Register Register Description Mnemonic Name EPA_MASK These registers enable/disable the 20 multiplexed EPA interrupts Interrupt EPA_MASK1 Mask Registers EPA_PEND The bits in these registers are set by hardware to indicate that a Interrupt multiplexed EPA interrupt is pending.
Page 100 STANDARD AND PTS INTERRUPTS Table 5-3. Interrupt Sources, Vectors, and Priorities Interrupt Controller PTS Service Service Interrupt Source Mnemonic † Nonmaskable Interrupt INT15 203EH — — — EXTINT Pin EXTINT INT14 203CH PTS14 205CH ††† CAN (CA) †† INT13 203AH PTS13 205AH Reserved (K x , J x )
Page 101: Special Interrupts
8XC196K x , J x , CA USER’S MANUAL 5.3.1 Special Interrupts This microcontroller has three special interrupt sources that are always enabled: unimplemented opcode, software trap, and NMI. These interrupts are not affected by the EI (enable interrupts) and DI (disable interrupts) instructions, and they cannot be masked. All of these interrupts are serviced by the interrupt controller;...
Page 102: Multiplexed Interrupt Sources
STANDARD AND PTS INTERRUPTS 5.3.3 Multiplexed Interrupt Sources Both the EPAx and CAN (CA only) interrupts are generated by a group of multiplexed interrupt sources. The EPA4–9 and COMP0–1 event interrupts, the EPA0–9 overrun interrupts, and the timer 1 and timer 2 overflow/underflow interrupts are multiplexed into EPAx. All CAN-controller interrupts are multiplexed into the single CAN interrupt.
Page 103: Situations That Increase Interrupt Latency
8XC196K x , J x , CA USER’S MANUAL When a standard interrupt request is acknowledged, the hardware clears the interrupt pending bit and forces a call to the address contained in the corresponding interrupt vector after completing the current instruction. The procedure that gets the vector and forces the call requires 11 state times.
Page 104: Calculating Latency
STANDARD AND PTS INTERRUPTS 5.4.2 Calculating Latency The maximum latency occurs when the interrupt request occurs too late for acknowledgment fol- lowing the current instruction. The following worst-case calculation assumes that the current in- struction is not a protected instruction. To calculate latency, add the following terms: •...
Page 105: Pts Interrupt Latency
8XC196K x , J x , CA USER’S MANUAL 5.4.2.2 PTS Interrupt Latency The maximum delay for a PTS interrupt is 43 state times (4 + 39). This delay time does not in- clude the added delay if a protected instruction is being executed or if a PTS request is already in progress.
Page 106: Programming The Interrupts
STANDARD AND PTS INTERRUPTS PROGRAMMING THE INTERRUPTS The PTS select register (PTSSEL) selects either PTS service or a standard software interrupt ser- vice routine for each of the maskable interrupt requests (see Figure 5-4). The interrupt mask reg- isters, INT_MASK and INT_MASK1, enable or disable (mask) individual interrupts (see Figures 5-5 and 5-6).
Page 107 8XC196K x , J x , CA USER’S MANUAL Address: PTSSEL Reset State: 0000H The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt requests. Setting a bit selects a PTS microcode routine; clearing a bit selects a standard interrupt service routine.
Page 108 STANDARD AND PTS INTERRUPTS Address: INT_MASK Reset State: The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupts. (The EI and DI instructions enable and disable servicing of all maskable interrupts.). INT_MASK is the low byte of the program status word (PSW). PUSHF or PUSHA saves the contents of this register onto the stack and then clears this register.
Page 109: Modifying Interrupt Priorities
8XC196K x , J x , CA USER’S MANUAL Address: INT_MASK1 Reset State: The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupts. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can be read from or written to as a byte register.
Page 110 STANDARD AND PTS INTERRUPTS SERIAL_RI_ISR: PUSHA ; Save PSW, INT_MASK, INT_MASK1, & WSR ; (this disables all interrupts) LDB INT_MASK1, #01000000B ; Enable EXTINT only ; Enable interrupt servicing ; Service the RI interrupt POPA ; Restore PSW, INT_MASK, INT_MASK1, & ;...
Page 111: Determining The Source Of An Interrupt
8XC196K x , J x , CA USER’S MANUAL At the end of the service routine, the POPA instruction restores the original contents of the PSW, INT_MASK, INT_MASK1, and WSR registers; any changes made to these registers during the interrupt service routine are overwritten. Because interrupt calls cannot occur immediately following a POPA instruction, the last instruction (RET) will execute before another interrupt call can occur.
Page 112 STANDARD AND PTS INTERRUPTS The EPA4–9 and COMP0–1 event interrupts, the EPA0–9 overrun interrupts, and the timer 1 and timer 2 overflow/underflow interrupts are multiplexed into EPAx. The interrupt service routine associated with EPAx must read the EPA interrupt pending registers (EPA_PEND and EPA_PEND1) to determine the source of the interrupt request (see Figure 10-14 on page 10-28 and Figure 10-15 on page 10-29).
Page 113: Initializing The Pts Control Blocks
8XC196K x , J x , CA USER’S MANUAL Address: INT_PEND1 Reset State: When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit.
Page 114: Specifying The Pts Count
STANDARD AND PTS INTERRUPTS Each PTS control block (PTSCB) requires eight data bytes in register RAM. The address of the first (lowest) byte is stored in the PTS vector table in special-purpose memory (see “Special-pur- pose Memory” on page 4-3). Figure 5-9 shows the PTSCB for each PTS mode. Unused PTSCB bytes can be used as extra RAM.
Page 115 8XC196K x , J x , CA USER’S MANUAL Address: PTSSRV Reset State: 0000H The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corre- sponding PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt.
Page 116: Selecting The Pts Mode
STANDARD AND PTS INTERRUPTS 5.6.2 Selecting the PTS Mode The second byte of each PTSCB is always an 8-bit value called PTSCON. Bits 5–7 select the PTS mode (Figure 5-11). The function of bits 0–4 differ for each PTS mode. Refer to the sections that describe each routine in detail to see the function of these bits.
Page 117 8XC196K x , J x , CA USER’S MANUAL PTS Single Transfer Mode Control Block In single transfer mode, the PTS control block contains a source and destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT). Unused Unused PTSDST (HI)
Page 118 STANDARD AND PTS INTERRUPTS PTS Single Transfer Mode Control Block (Continued) Register Location Function PTSCON PTSCB + 1 PTS Control Bits M2:0 PTS Mode single transfer mode Byte/Word Transfer 0 = word transfer 1 = byte transfer † Update PTSSRC 0 = reload original PTS source address after each byte or word transfer 1 = retain current PTS source address after each byte or word...
Page 119: Block Transfer Mode
8XC196K x , J x , CA USER’S MANUAL Table 5-5. Single Transfer Mode PTSCB Unused Unused PTSDST (HI) = 60H PTSDST (LO) = 00H PTSSRC (HI) = 00H PTSSRC (LO) = 20H PTSCON = 85H (Mode = 100, DI & DU = 1, BW = 0) PTSCOUNT = 09H 5.6.4 Block Transfer Mode...
Page 120 STANDARD AND PTS INTERRUPTS PTS Block Transfer Mode Control Block In block transfer mode, the PTS control block contains a block size (PTSBLOCK), a source and destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT). Unused PTSBLOCK PTS Block Size...
Page 121: A/D Scan Mode
8XC196K x , J x , CA USER’S MANUAL PTS Block Transfer Mode Control Block (Continued) Register Location Function PTSCON PTSCB + 1 PTS Control Bits M2:0 PTS Mode These bits select the PTS mode: block transfer mode Byte/Word Transfer 0 = word transfer 1 = byte transfer Update PTSSRC...
Page 122 STANDARD AND PTS INTERRUPTS PTS A/D Scan Mode Control Block In A/D scan mode, the PTS causes the A/D converter to perform multiple conversions on one or more channels and then stores the results. The control block contains pointers to both the AD_RESULT register and a table of A/D conversion commands and results (PTSPTR1 and PTSPTR2), a control register (PTSCON), and a A/D conversion count (PTSCOUNT).
Page 123 8XC196K x , J x , CA USER’S MANUAL PTS A/D Scan Mode Control Block (Continued) PTSCOUNT PTSCB + 0 Consecutive A/D Conversions Defines the number of A/D conversions that will be completed during the A/D scan routine. Each cycle consists of the PTS transferring the A/D conversion results into the command/data table, and then loading a new command into the AD_COMMAND register.
Page 124: A/D Scan Mode Cycles
STANDARD AND PTS INTERRUPTS 5.6.5.1 A/D Scan Mode Cycles Software must start the first A/D conversion. After the A/D conversion complete interrupt ini- tiates the PTS routine, the following actions occur. The PTS reads the first command, stores it in a temporary location, and increments the PTSPTR1 register twice.
Page 125: A/D Scan Mode Example 2
8XC196K x , J x , CA USER’S MANUAL version. Step 4 updates PTSPTR1 (PTSPTR1 now points to 3004H) and step 5 decrements PTSCOUNT to 3. The next cycle begins by storing the channel 5 command in the temporary lo- cation.
Page 126: Pwm Modes
STANDARD AND PTS INTERRUPTS Table 5-11. A/D Scan Mode PTSCB (Example 2) Unused Unused PTSPTR2 (HI) = 1FH PTSPTR2 (LO) = AAH PTSPTR1 (HI) = 30H PTSPTR1 (LO) = 00H PTSCON = C3H (Mode = 110, UPDT = 0) PTSCOUNT = 0AH Software starts a conversion on channel x.
Page 127: Pwm Toggle Mode Example
8XC196K x , J x , CA USER’S MANUAL Figure 5-15 illustrates a generic PWM waveform. The time the output is “on” is T1; the time the output is “off” is T2 – T1. The formulas for frequency and duty cycle are shown below. In most applications, the frequency is held constant and the duty cycle is varied to change the average val- ue of the waveform.
Page 128 STANDARD AND PTS INTERRUPTS Set up the PTSCB as shown in Table 5-13: — Load PTSCON with 43H (selects PWM toggle mode, initial TBIT value = 1) — Set up PTSPTR1 to point to EPA0_TIME (the EPA0 event-time register) — Load PTSCONST1 with the on-time (T1) from CSTORE1. —...
Page 129 8XC196K x , J x , CA USER’S MANUAL PTS PWM Toggle Mode Control Block In PWM toggle mode, the PTS uses a single EPA channel to generate a pulse-width modulated (PWM) output signal. The control block contains registers that contain the PWM on-time (PTSCONST1), the PWM off-time (PTSCONST2), the address pointer (PTSPTR1), and a control register (PTSCON).
Page 130 STANDARD AND PTS INTERRUPTS PTS PWM Toggle Mode Control Block (Continued) Register Location Function PTSCON PTSCB + 1 PTS Control Bits M2:0 PTS Mode These bits specify the PTS mode: TMOD Toggle Mode Select 1 = PWM toggle mode TBIT Toggle Bit Initial Value Determines the initial value of TBIT.
Page 131 8XC196K x , J x , CA USER’S MANUAL Start Start Timer Timer Match Match Toggle Output Toggle Output PTS Cycle TBIT TBIT EPA0_TIME = EPA0_TIME + (T2 - T1) EPA0_TIME = EPA0_TIME + (T2 - T1) EPA0_TIME = EPA0_TIME + T1 EPA0_TIME = EPA0_TIME + T1 Toggle TBIT Toggle TBIT...
Page 132: Pwm Remap Mode Example
STANDARD AND PTS INTERRUPTS When the next timer match occurs, the PTS cycle (Figure 5-17) increments EPA0_TIME by T1 (if TBIT is zero (output = 0)) or T2 – T1 (if TBIT is one (output = 1)). (Note that although the values of the EPA0 output and TBIT are the same in this example, these two values are unrelated.
Page 133 8XC196K x , J x , CA USER’S MANUAL Table 5-14. PWM Remap Mode PTSCB PTSCB0 for EPA0 PTSCB1 for EPA1 Unused Unused Unused Unused PTSCONST1 (HI) = T2 (HI) PTSCONST1 (HI) = T2 (HI) PTSCONST1 (LO) = T2 (LO) PTSCONST1 (LO) = T2 (LO) PTSPTR1 (HI) = 1FH (EPA0_TIME, HI) PTSPTR1 (HI) = 1FH (EPA1_TIME, HI)
Page 134 STANDARD AND PTS INTERRUPTS PTS PWM Remap Mode Control Block In PWM remap mode, the PTS uses two EPA channels to generate a pulse-width modulated (PWM) output signal. The control block contains registers that contain the PWM on-time (PTSCONST1), the address pointer (PTSPTR1), and a control register (PTSCON).
Page 135 8XC196K x , J x , CA USER’S MANUAL PTS PWM Remap Mode Control Block (Continued) Register Location Function PTSCON PTSCB + 1 PTS Control Bits M2:0 PTS Mode These bits specify the PTS mode: TMOD Remap Mode Select 0 = PWM remap mode TBIT Toggle Bit Initial Value Determines the initial value of TBIT.
Page 136 STANDARD AND PTS INTERRUPTS Start Start Timer Timer Match Match If EPA0, set the output If EPA0, set the output If EPA1, clear the output If EPA1, clear the output PTS Cycle If EPA0: EPA0_TIME = EPA0_TIME + T2 If EPA0: EPA0_TIME = EPA0_TIME + T2 If EPA1: EPA1_TIME = EPA1_TIME + T2 If EPA1: EPA1_TIME = EPA1_TIME + T2 Toggle TBIT...
Page 138: I/O Ports
I/O Ports...
Page 140: I/O Ports Overview
CHAPTER 6 I/O PORTS I/O ports provide a mechanism to transfer information between the device and the surrounding system circuitry. They can read system status, monitor system operation, output device status, configure system options, generate control signals, provide serial communication, and so on. Their usefulness in an application is limited only by the number of I/O pins available and the imagination of the engineer.
Page 141: Standard Input-Only Port Operation
8XC196K x , J x , CA USER’S MANUAL Because port 0 is permanently configured as an input-only port, it has no configuration registers. Its single register, P0_PIN, can be read to determine the current state of the pin. The register is byte-addressable and can be windowed.
Page 142: Standard Input-Only Port Considerations
I/O PORTS Internal Bus To Analog MUX PORT 0 Level Data Register Translation Buffer Buffer P0_PIN Input Pin 150 to 200 Ohms Read Port PH1 Clock ANGND ANGND A0236-01 Figure 6-1. Standard Input-only Port Structure 6.2.2 Standard Input-only Port Considerations Port 0 pins are unique in that they may individually be used as digital inputs and analog inputs at the same time.
Page 143: Bidirectional Ports 1, 2, 5, And 6
8XC196K x , J x , CA USER’S MANUAL BIDIRECTIONAL PORTS 1, 2, 5, AND 6 Although the bidirectional ports are very similar in both circuitry and configuration, port 5 differs from the others in some ways. Port 5, a memory-mapped port, uses a standard CMOS input buffer because of the high speeds required for system control functions.
Page 144 I/O PORTS Table 6-4. Bidirectional Port Pins (Continued) Special-function Special-function Associated Port Pin Signal(s) Signal Type Peripheral INST Bus controller † P5.1 SLPCS# Slave port WR#/WRL# Bus controller P5.2 SLPWR# Slave port Bus controller P5.3 SLPRD# Slave port ††† ††† P5.4 SLPINT Slave port...
Page 145: Bidirectional Port Operation
8XC196K x , J x , CA USER’S MANUAL Table 6-5. Bidirectional Port Control and Status Registers (Continued) Mnemonic Address Description P1_MODE 1FD0H Port x Mode P2_MODE 1FC9H Each bit of P x _MODE controls whether the corresponding pin P5_MODE 1FF1H functions as a standard I/O port pin or as a special-function signal.
Page 146 I/O PORTS Resistor R1 provides ESD protection for the pin. Input signals are buffered. The standard ports use Schmitt-triggered buffers for improved noise immunity. Port 5 uses a standard input buffer because of the high speeds required for system control functions. The signals are latched into the Px_PIN sample latch and output onto the internal bus when the Px_PIN register is read.
Page 147 8XC196K x , J x , CA USER’S MANUAL Internal Bus Px_REG SFDATA I/O Pin Px_DIR SFDIR Px_MODE Sample 150Ω to 200Ω Latch Px_PIN Read Port PH1 Clock Medium Pullup 300ns Delay RESET# Weak RESET# Pullup Any Write to Px_MODE A0238-04 Figure 6-2.
Page 148 I/O PORTS Table 6-6. Logic Table for Bidirectional Ports in I/O Mode Open-drain Configuration Complementary Output Input Output P x _MODE P x _DIR SFDIR SFDATA P x _REG 0, 1 (Note 2) on, off (Note 2) P x _PIN X (Note 3) high-impedance (Note 4) NOTES:...
Page 149: Bidirectional Port Pin Configurations
8XC196K x , J x , CA USER’S MANUAL 6.3.2 Bidirectional Port Pin Configurations Each bidirectional port pin can be individually configured to operate either as an I/O pin or as a pin for a special-function signal. In the special-function configuration, the signal is controlled by an on-chip peripheral or an off-chip component.
Page 150: Bidirectional Port Pin Configuration Example
I/O PORTS Table 6-8. Control Register Values for Each Configuration Desired Pin Configuration Configuration Register Settings † Standard I/O Signal P x _DIR P x _MODE P x _REG Complementary output, driving 0 Complementary output, driving 1 Open-drain output, strongly driving 0 Open-drain output, high-impedance Input †...
Page 151: Bidirectional Port Considerations
8XC196K x , J x , CA USER’S MANUAL Table 6-10. Port Pin States After Reset and After Example Code Execution † Resulting Pin States Action or Code Px.7 Px.6 Px.5 Px.4 Px.3 Px.2 Px.1 Px.0 Reset LDB P x _DIR, #00011111B LDB P x _MODE, #00000000B LDB P x _REG, #10010011B †...
Page 152 P2.6/HLDA# is the enable pin for ONCE mode in certain 8XC196Kx devices (see Chapter 14, “Special Operating Modes”) and one of the enable pins for Intel-reserved test modes. Because a low input during reset could cause the device to enter ONCE mode or a reserved test mode, exercise caution if you use this pin for input.
Page 153 P5_MODE. P5.4/SLPINT is the enable pin for ONCE mode in certain 8XC196Kx devices (see Chapter 14, “Special Operating Modes”) and one of the enable pins for Intel-reserved test modes. Because a low input during reset could cause the device to enter ONCE mode or a reserved test mode, exercise caution if you use this pin for input.
Page 154: Design Considerations For External Interrupt Inputs
I/O PORTS P6.4–P6.7 A value written to any of the upper four bits of P6_REG (bits 4–7) is held in a buffer until the corresponding P6_MODE bit is cleared, at which time the value is loaded into the P6_REG bit. A value read from a P6_REG bit is the value currently in the register, not the value in the buffer.
Page 155: Bidirectional Ports 3 And 4 (Address/Data Bus) Operation
8XC196K x , J x , CA USER’S MANUAL Table 6-11 lists the port 3 and 4 pins with their special-function signals and associated peripher- als. Table 6-12 lists the registers that affect the function and indicate the status of ports 3 and 4. Table 6-11.
Page 156 I/O PORTS Internal Bus Px_REG ADDRESS/DATA I/O Pin BUS CONTROL SELECT 0=Address/Data 1=I/O P34_DRV RESET# Sample 150Ω to 200Ω Latch Px_PIN Buffer Read Port PH1 Clock Medium Pullup 300ns Delay RESET# Weak Pullup A0240-03 Figure 6-3. Address/Data Bus (Ports 3 and 4) Structure When external memory access is not required, the device sets BUS CONTROL SELECT, select- ing Px_REG as the input to the multiplexer.
Page 157: Using Ports 3 And 4 As I/O
8XC196K x , J x , CA USER’S MANUAL With the open-drain configuration (BUS CONTROL SELECT set and P34_DRV cleared) and Px_REG set, the pin can be used as an input. The signal on the pin is latched in the Px_PIN reg- ister.
Page 158: Design Considerations For Ports 3 And 4
I/O PORTS 6.4.3 Design Considerations for Ports 3 and 4 When EA# is active, ports 3 and 4 will function only as the address/data bus. In these circum- stances, an instruction that operates on P3_REG or P4_REG causes a bus cycle that reads from or writes to the external memory location corresponding to the SFR’s address.
Page 160: Serial I/O (Sio) Port
Serial I/O (SIO) Port...
Page 162: Serial I/O (Sio) Port Functional Overview
CHAPTER 7 SERIAL I/O (SIO) PORT A serial input/output (SIO) port provides a means for the system to communicate with external devices. This device has a serial I/O (SIO) port that shares pins with port 2. This chapter describes the SIO port and explains how to configure it. Chapter 6, “I/O Ports,” explains how to configure the port pins for their special functions.
Page 163: Serial I/O Port Signals And Registers
8XC196K x , J x , CA USER’S MANUAL An independent, 15-bit baud-rate generator controls the baud rate of the serial port. Either XTAL1 or T1CLK can provide the clock signal. The baud-rate register (SP_BAUD) selects the clock source and the baud rate. SERIAL I/O PORT SIGNALS AND REGISTERS Table 7-1 describes the SIO signals and Table 7-2 describes the control and status registers.
Page 164 SERIAL I/O (SIO) PORT Table 7-2. Serial Port Control and Status Registers (Continued) † Mnemonic Address Description P2_DIR 1FCBH Port 2 Direction This register selects the direction of each port 2 pin. Clear P2_DIR.1 to configure RXD (P2.1) as a high-impedance input/open-drain output, and set P2_DIR.0 to configure TXD (P2.0) as a comple- mentary output.
Page 165: Serial Port Modes
8XC196K x , J x , CA USER’S MANUAL Table 7-2. Serial Port Control and Status Registers (Continued) † Mnemonic Address Description SP_BAUD 1FBCH,1FBDH Serial Port Baud Rate This register selects the serial port baud rate and clock source. The most-significant bit selects the clock source.
Page 166 SERIAL I/O (SIO) PORT During a reception, the RI flag in SP_STATUS is set after the stop bit is sampled. The RI pending bit in the interrupt pending register is set immediately before the RI flag is set. During a transmis- sion, the TI flag is set immediately after the end of the last (eighth) data bit is transmitted.
Page 167: Asynchronous Modes (Modes 1, 2, And 3)
8XC196K x , J x , CA USER’S MANUAL 7.3.2 Asynchronous Modes (Modes 1, 2, and 3) Modes 1, 2, and 3 are full-duplex serial transmit/receive modes, meaning that they can transmit and receive data simultaneously. Mode 1 is the standard 8-bit, asynchronous mode used for nor- mal serial communications.
Page 168: Mode 2
SERIAL I/O (SIO) PORT Use caution when connecting more than two devices with the serial port in half-duplex (i.e., with one wire for transmit and receive). The receiving processor must wait for one bit time after the RI flag is set before starting to transmit. Otherwise, the transmission could corrupt the stop bit, causing a problem for other devices listening on the link.
Page 169: Multiprocessor Communications
8XC196K x , J x , CA USER’S MANUAL 7.3.2.5 Multiprocessor Communications Modes 2 and 3 are provided for multiprocessor communications. In mode 2, the serial port sets the RI interrupt pending bit only when the ninth data bit is set. In mode 3, the serial port sets the RI interrupt pending bit regardless of the value of the ninth bit.
Page 170 SERIAL I/O (SIO) PORT Address: 1FBBH SP_CON Reset State: The serial port control (SP_CON) register selects the communications mode and enables or disables the receiver, parity checking, and nine-bit data transmission. CA, J x , KQ, KR — — — KS, KT —...
Page 171: Programming The Baud Rate And Clock Source
8XC196K x , J x , CA USER’S MANUAL 7.4.3 Programming the Baud Rate and Clock Source The SP_BAUD register (Figure 7-7) selects the clock input for the baud-rate generator and de- fines the baud rate for all serial I/O modes. This register acts as a control register during write operations and as a down-counter monitor during read operations.
Page 172 SERIAL I/O (SIO) PORT Address: 1FBCH SP_BAUD (Continued) Reset State: 0000H The serial port baud rate (SP_BAUD) register selects the serial port baud rate and clock source. The most-significant bit selects the clock source. The lower 15 bits represent BAUD_VALUE, an unsigned integer that determines the baud rate.
Page 173: Enabling The Serial Port Interrupts
8XC196K x , J x , CA USER’S MANUAL CAUTION For mode 0 receptions, the BAUD_VALUE must be 0002H or greater. Otherwise, the resulting data in the receive shift register will be incorrect. The reason for this restriction is that the receive shift register is clocked from an internal signal rather than the signal on TXD.
Page 174: Determining Serial Port Status
SERIAL I/O (SIO) PORT 7.4.5 Determining Serial Port Status You can read the SP_STATUS register (Figure 7-8) to determine the status of the serial port. Reading SP_STATUS clears all bits except TXE. For this reason, we recommend that you copy the contents of the SP_STATUS register into a shadow register and then execute bit-test instruc- tions such as JBC and JBS on the shadow register.
Page 175: Programming Example Using An Interrupt-Driven Routine
8XC196K x , J x , CA USER’S MANUAL The receiver checks for a valid stop bit. Unless a stop bit is found within the appropriate time, the framing error (FE) bit in the SP_STATUS register is set. When the stop bit is detected, the data in the receive shift register is loaded into SBUF_RX and the receive interrupt (RI) flag is set.
Page 176 SERIAL I/O (SIO) PORT #define TRANSMIT_BUF_SIZE 20 #define RECEIVE_BUF_SIZE 20 #define WINDOW_SELECT 0x1F #define FREQUENCY (long)16000000 /* 16 MHz #define BAUD_RATE_VALUE 9600 #define BAUD_REG ((unsigned int)(FREQUENCY/((long)BAUD_RATE_VALUE*16)-1)+0x8000) #define RI_BIT 0x40 #define TI_BIT 0x20 unsigned char status_temp; image of SP_STATUS to preserve the RI and TI bits on a read. receive and transmit buffers and their indexes unsigned char trans_buff[TRANSMIT_BUF_SIZE];...
Page 177 8XC196K x , J x , CA USER’S MANUAL void receive(void) serial interrupt routine wsr = WINDOW_SELECT; status_temp |= SP_STATUS; image SP_STATUS into status_temp If the input buffer is full, the last character will be ignored, and the BEL character is output to the terminal. if(end_rec_buff+1==begin_rec_buff || (end_rec_buff==RECEIVE_BUF_SIZE-1 &&...
Page 178 SERIAL I/O (SIO) PORT port2_reg 0xFF; Init port2 reg */ port2_dir &= 0xFE; TXD output port2_mode |= 0x03; p2.4-6 lsio wsr=0; end_rec_buff=0; /* initialize buffer pointers begin_rec_buff=0; end_trans_buff=0; begin_trans_buff=0; status_temp = TI_BIT; /* allow for initial transmission int_mask1=0x18; /* enable the serial port interrupt enable();...
Page 180: Synchronous Serial I/O (Ssio) Port
Synchronous Serial I/O (SSIO) Port...
Page 182: Synchronous Serial I/O (Ssio) Port Functional Overview
CHAPTER 8 SYNCHRONOUS SERIAL I/O (SSIO) PORT This device has a synchronous serial I/O (SSIO) port that shares pins with port 6. This chapter describes the SSIO port and explains how to program it. Chapter 6, “I/O Ports,” explains how to configure the port pins for their special functions.
Page 183: Ssio Port Signals And Registers
8XC196K x , J x , CA USER’S MANUAL SSIO PORT SIGNALS AND REGISTERS Table 8-1 describes the SSIO signals and Table 8-2 describes the control and status registers. Table 8-1. SSIO Port Signals SSIO Port SSIO Port Port Description Signal Type Signal P6.4...
Page 184: Ssio Operation
SYNCHRONOUS SERIAL I/O (SSIO) PORT Table 8-2. SSIO Port Control and Status Registers (Continued) Mnemonic Address Description INT_PEND1 0012H Interrupt Pending 1 When set, SSIO0 indicates a pending channel 0 transfer interrupt. When set, SSIO1 indicates a pending channel 1 transfer interrupt. P6_DIR 1FD2H Port 6 Direction This register selects the direction of each port 6 pin.
Page 185 8XC196K x , J x , CA USER’S MANUAL Master Slave Single-channel Half-duplex Master/Slave Configuration Master Slave Slave Slave Double-channel Full-duplex Lockstep Common Clock Configuration Master Slave Slave Master Double-channel Full-duplex Master/Slave Separate Clock Configuration A0233-03 Figure 8-2. SSIO Operating Modes •...
Page 186 SYNCHRONOUS SERIAL I/O (SSIO) PORT • The two channels can operate together, from the same clock, as master transceivers to communicate in lockstep (mutually synchronous), full-duplex mode. This mode requires one data input pin, one data output pin, and two clock pins (the clock output pin from one channel connected to the clock input pin of the other).
Page 187: Ssio Handshaking
8XC196K x , J x , CA USER’S MANUAL SC x SD x (out) SD x (in) valid valid valid valid valid valid valid valid SC x (Handshake Mode) Slave Receiver Pulls SC x low A0266-01 Figure 8-3. SSIO Transmit/Receive Timings SSIO HANDSHAKING Handshaking (Figure 8-4) prevents a data underflow or overflow from occurring at the slave, which enables a master device to perform SSIO data transfers using the PTS.
Page 188: Ssio Handshaking Operation
SYNCHRONOUS SERIAL I/O (SSIO) PORT Load SSIO x _BUF Receive Byte Pull SC Pin Low SC x Pin High SSIO x _BUF Read Transmit Byte Set SSIO x Interrupt Float SC x Pin Pending Bit SSIO Transmit Handshaking SSIO Receive Handshaking A0232-03 Figure 8-4.
Page 189 8XC196K x , J x , CA USER’S MANUAL The following example describes how the master can transmit 16 bytes of data to the slave through the PTS, using this optional handshaking capability. These four steps can occur in any order: —...
Page 190: Programming The Ssio Port
SYNCHRONOUS SERIAL I/O (SSIO) PORT PROGRAMMING THE SSIO PORT To use the SSIO port, you must configure the port pins to serve as special-function signals, then set up the SSIO channels. 8.5.1 Configuring the SSIO Port Pins Before you can use the SSIO port, you must configure the necessary port 6 pins to serve as their special-function signals.
Page 191: Controlling The Communications Mode And Handshaking
8XC196K x , J x , CA USER’S MANUAL Address: 1FB4H SSIO_BAUD Reset State: The synchronous serial port baud (SSIO_BAUD) register enables and disables the baud-rate generator and selects the SSIO baud rate. During read operations, SSIO_BAUD serves as the down- counter monitor.
Page 192 SYNCHRONOUS SERIAL I/O (SSIO) PORT Address: 1FB1H, 1FB3H SSIO x _CON Reset State: x = 0–1 The synchronous serial control x (SSIO x _CON) registers control the communications mode and handshaking. The two least-significant bits indicate whether an overflow or underflow has occurred and whether the channel is ready to transmit or receive.
Page 193 8XC196K x , J x , CA USER’S MANUAL Address: 1FB1H, 1FB3H SSIO x _CON (Continued) Reset State: x = 0–1 The synchronous serial control x (SSIO x _CON) registers control the communications mode and handshaking. The two least-significant bits indicate whether an overflow or underflow has occurred and whether the channel is ready to transmit or receive.
Page 194: Enabling The Ssio Interrupts
SYNCHRONOUS SERIAL I/O (SSIO) PORT 8.5.4 Enabling the SSIO Interrupts Each SSIO channel can generate an interrupt request if you enable the individual interrupt as well as globally enabling servicing of all maskable interrupts. The INT_MASK1 register enables and disables individual interrupts. To enable an SSIO interrupt, set the corresponding bit in INT_MASK1 (see Table 8-2 on page 8-2) and execute the EI instruction to globally enable inter- rupt servicing.
Page 195 8XC196K x , J x , CA USER’S MANUAL Clock (SC x pin) "1" "0" "1" "0" "0" Data (SD x pin) A2066-01 Figure 8-7. Variable-width MSB in SSIO Transmissions NOTE This condition exists only for the MSB. Once the MSB is clocked out, the remaining bits are clocked out consistently at the programmed frequency.
Page 196: Programming Example
SYNCHRONOUS SERIAL I/O (SSIO) PORT PROGRAMMING EXAMPLE This code example configures SSIO0 as a master transmitter to send one byte of data to SSIO1, the slave receiver. First it sets up a window to allow register-direct access to the necessary regis- ters.
Page 198: Slave Port
Slave Port...
Page 200 CHAPTER 9 SLAVE PORT The slave port offers an alternative for communication between two microcontrollers. Tradition- ally, design engineers have had three options for achieving this communication — a serial link, a parallel bus without a dual-port RAM (DPRAM), or a parallel bus with a DPRAM to hold shared data.
Page 201: Slave Port Functional Overview
8XC196K x , J x , CA USER’S MANUAL Processor A Dual-port Processor B (Master) (Slave) (DPRAM) Slave Processor A (Master) On-chip 8XC196 Device A3065-01 Figure 9-1. DPRAM vs Slave-Port Solution SLAVE PORT FUNCTIONAL OVERVIEW Figure 9-2 is a block diagram of the slave port. The slave port is a simple bus configuration that can interface to an external processor through an 8-bit address/data bus (SLP7:0).
Page 202 SLAVE PORT SLP_STAT.0 SLPINT/ P5.4 SLP_STAT.1 SLPALE /P5.0 SLP_CON.2 SLP_CON SLP_ADDR SLP1/P3.1 SLPRD# /P5.3 SLPWR# /P5.2 SLP_STAT SLPCS# P3_REG P5.1 (Data Out) P3_PIN (Data In) SLP7:0/ SLP_CMD P3.7:0 Internal 8XC196 Device A0267-03 Figure 9-2. Slave Port Block Diagram...
Page 203 8XC196K x , J x , CA USER’S MANUAL Table 9-1. Slave Port Signals Slave Slave Port Port Pin Port Description Signal Type Signal P3.7:0 SLP7:0 Slave Port Address/Data bus Slave port address/data bus in multiplexed mode and slave port data bus in demultiplexed mode.
Page 204 SLAVE PORT Table 9-2. Slave Port Control and Status Registers (Continued) Mnemonic Address Description INT_PEND1 Interrupt Pending 1 Bit 0, when set, indicates a pending command buffer full (CBF) interrupt. This bit is set after the master writes to the command register, SLP_CMD.
Page 205: Hardware Connections
8XC196K x , J x , CA USER’S MANUAL HARDWARE CONNECTIONS Figure 9-3 shows the basic hardware connections for both multiplexed and demultiplexed bus modes. Table 9-3 lists the interconnections. Note that the shared memory mode (8XC196KS and KT only) supports only a multiplexed bus, while the standard slave mode supports either a mul- tiplexed or a demultiplexed bus.
Page 206 SLAVE PORT Slave Interrupt Output SLPINT Data Read (RD#) SLPRD# Data Write (WR#) SLPWR# Address Latch Enable (ALE) SLPALE Latched Address Decoder Chip Select (CS#) SLPCS# Master Processor SLP7:0 Address/Data Bus or System Bus 8XC196 Slave Processor Slave Port Connections for Multiplexed Bus Interface Slave Interrupt Output SLPINT Data Read (RD#)
Page 207: Slave Port Modes
8XC196K x , J x , CA USER’S MANUAL SLAVE PORT MODES The slave port can operate in either standard slave mode or shared memory mode (8XC196KS and KT only). In both modes, the master and slave share a 256-byte block of memory located any- where within the slave’s memory space.
Page 208: Slave Device Program
SLAVE PORT The master first reads the P3_REG register. This ensures that the slave’s P3_REG is indeed emp- ty, clears the OBF flag, and pulls SLPINT low. Next, it loads the address it wants to read into the SLP_CMD register. This causes a CBF interrupt in the slave processor. The slave reads that lo- cation and stores the data in P3_REG, which sets the OBF flag and forces SLPINT high.
Page 209: Demultiplexed Bus Timings
8XC196K x , J x , CA USER’S MANUAL READ_DATA: TEMPW, [MAILBOX] ; get data to write to P3_REG TEMPW, P3_REG[0] ; write SLP_CMD+400H data to P3_REG POPA 9.4.1.3 Demultiplexed Bus Timings The master processor performs two bus cycles for each byte written and three bus cycles for each byte read.
Page 210: Shared Memory Mode Example (8Xc196Ks And Kt Only)
SLAVE PORT 9.4.2 Shared Memory Mode Example (8XC196KS and KT only) In shared memory mode, the master and slave share a 256-byte block of memory. The high byte of the address (the base address) controls the location within the slave device memory space. The low byte of the address is always in the SLP_CMD register.
Page 211: Slave Device Program
8XC196K x , J x , CA USER’S MANUAL 9.4.2.2 Slave Device Program This example shows how the slave device reacts to reads and writes requested by the master. Re- gardless of the operation to be performed, the address is latched into the SLP_CMD register. The interrupt determines whether a read or write operation is to be performed.
Page 212: Multiplexed Bus Timings
SLAVE PORT 9.4.2.3 Multiplexed Bus Timings The memory space required for the sample code is four bytes (two bytes for the address register, one for the temp register, and one for the base address). Reads and writes each require 58 state times (7.25 µs at 16 MHz).
Page 213: Configuring The Slave Port
8XC196K x , J x , CA USER’S MANUAL CONFIGURING THE SLAVE PORT Before you can use the slave port, you must configure the associated port 3 and port 5 pins to serve as special-function signals. (See Chapter 6, “I/O Ports,” for configuration details.) •...
Page 214 SLAVE PORT Address: 1FFBH SLP_CON Reset State: (8XC196K x ) The slave port control (SLP_CON) register is used to configure the slave port. Only the slave can access the register. KQ, KR — — — — SLPL IBEMSK OBFMSK KS, KT —...
Page 215: Enabling The Slave Port Interrupts
8XC196K x , J x , CA USER’S MANUAL 9.5.2 Enabling the Slave Port Interrupts The master can generate three interrupt requests: command buffer full (CBF), output buffer emp- ty (OBE), and input buffer full (IBF). The CBF interrupt is used in standard slave mode; the OBE and IBF interrupts are used in shared memory mode.
Page 216 SLAVE PORT Address: 1FF8H SLP_STAT Reset State: (8XC196K x ) The master can read the slave port status (SLP_STAT) register to determine the status of the slave. The slave can read all bits and can write bits 3–7 for general-purpose status information. (The bits are user-defined flags.) If the master attempts to write to SLP_STAT, it actually writes to SLP_CMD.
Page 218: Event Processor Array (Epa)
Event Processor Array (EPA)
Page 220: Epa Functional Overview
CHAPTER 10 EVENT PROCESSOR ARRAY (EPA) Control applications often require high-speed event control. For example, the controller may need to periodically generate pulse-width modulated outputs, an analog-to-digital conversion, or an in- terrupt. In another application, the controller may monitor an input signal to determine the status of an external device.
Page 221: Epa And Timer/Counter Signals And Registers
8XC196K x , J x , CA USER’S MANUAL Timer-Counter Unit TIMER1 TIMER2 Capture/Compare EPA 3:0 Interrupts Channel 0–3 EPA 3:0 8XC196K x Only Capture/Compare Channel 4–7 EPA7:4 Capture/Compare EPA8 / COMP0 Channel 8 EPA x Interrupt Indirect Compare-only Interrupt Channel 0 Processor Logic...
Page 222 EVENT PROCESSOR ARRAY (EPA) Table 10-2. EPA and Timer/Counter Signals Port Pin EPA Signal(s) Description Signal Type P1.0 EPA0 High-speed input/output for capture/compare channel 0. T2CLK External clock source for timer 2. If you use T2CLK, you cannot use capture/compare channel P1.1 EPA1 High-speed input/output for capture/compare...
Page 223 8XC196K x , J x , CA USER’S MANUAL Table 10-3. EPA Control and Status Registers (Continued) Mnemonic Address Description EPA_PEND1 1FA6H EPA Interrupt Pending 1 Any set bit in this register indicates a pending interrupt. EPA x Capture/Compare Control EPA0_CON 1F60H EPA1_CON...
Page 224 EVENT PROCESSOR ARRAY (EPA) Table 10-3. EPA Control and Status Registers (Continued) Mnemonic Address Description P1_PIN 1FD6H Port x Input P6_PIN 1FD7H Each bit of P x _PIN reflects the current state of the corresponding pin, regardless of the pin configuration. Port x Data Output P1_REG 1FD4H...
Page 225: Timer/Counter Functional Overview
8XC196K x , J x , CA USER’S MANUAL 10.3 TIMER/COUNTER FUNCTIONAL OVERVIEW The EPA has two 16-bit up/down timer/counters, timer 1 and timer 2, which can be clocked in- ternally or externally. Each is called a timer if it is clocked internally and a counter if it is clocked externally.
Page 226: Cascade Mode (Timer 2 Only)
EVENT PROCESSOR ARRAY (EPA) The timer/counters can be used as time bases for input captures, output compares, and pro- grammed interrupts (software timers). When a counter increments from FFFEH to FFFFH or dec- rements from 0001H to 0000H, the counter-overflow interrupt pending bit is set. This bit can optionally cause an interrupt.
Page 227 8XC196K x , J x , CA USER’S MANUAL Increment 8XC196 Device Decrement T x CLK X_internal Optical Reader T x DIR Y_internal A0268-02 Figure 10-3. Quadrature Mode Interface Table 10-4. Quadrature Mode Truth Table State of X_internal State of Y_internal Count Direction (T x CLK) (T x DIR)
Page 228: Epa Channel Functional Overview
EVENT PROCESSOR ARRAY (EPA) CLKOUT T x CLK T x DIR COUNT x + 1 x + 2 x + 3 x + 4 x + 5 x + 6 x + 5 x + 4 x + 3 x + 2 x + 1 A0269-02 Figure 10-4.
Page 229 8XC196K x , J x , CA USER’S MANUAL Each EPA channel has a control register, EPAx_CON (capture/compare channels) or COMPx_CON (compare-only channels); an event-time register, EPAx_TIME (capture/compare channels) or COMPx_TIME (compare-only channels); and a timer input (Figure 10-5). The con- trol register selects the timer, the mode, and either the event to be captured or the event that is to occur.
Page 230: Operating In Capture Mode
EVENT PROCESSOR ARRAY (EPA) 10.4.1 Operating in Capture Mode In capture mode, when a valid event occurs on the pin, the value of the selected timer is captured into a buffer. The timer value is then transferred from the buffer to the EPAx_TIME register, which sets the EPA interrupt pending bit as shown in Figure 10-6.
Page 231: Handling Epa Overruns
8XC196K x , J x , CA USER’S MANUAL Event 1 2 State 2 State Times Times Event 2 2 State 2 State Times Times A3130-01 Figure 10-7. Valid EPA Input Events Table 10-5. Action Taken when a Valid Edge Occurs Status of Overwrite Bit Capture Buffer...
Page 232: Operating In Compare Mode
EVENT PROCESSOR ARRAY (EPA) The input frequency at which this occurs depends on the length of the interrupt service routine as well as other factors. Unless the interrupt service routine includes a check for overruns, this situ- ation will remain the same until the device is reset or the EPAx_TIME register is read. The act of reading EPAx_TIME allows the buffered time value to be moved into EPAx_TIME.
Page 233: Generating A Low-Speed Pwm Output
8XC196K x , J x , CA USER’S MANUAL 10.4.2.1 Generating a Low-speed PWM Output You can generate a low-speed, pulse-width modulated output with a single EPA channel and a standard interrupt service routine. Configure the EPA channel as follows: compare mode, toggle output, and the compare function re-enabled.
Page 234: Generating A Medium-Speed Pwm Output
EVENT PROCESSOR ARRAY (EPA) The worst-case interrupt latency for a single-interrupt system is 56 state times for external stack usage and 54 state times for internal stack usage (see “Standard Interrupt Latency” on page 5-9). To determine the execution time for an interrupt service routine, add up the execution time of the instructions in the ISR (Table A-9).
Page 235: Generating A High-Speed Pwm Output
8XC196K x , J x , CA USER’S MANUAL The worst-case interrupt latency for a single-interrupt system with PTS service is 43 state times (see “PTS Interrupt Latency” on page 5-10). The PTS cycle execution time in PWM toggle mode is 15 state times (Table 5-4 on page 5-10).
Page 236: Programming The Epa And Timer/Counters
EVENT PROCESSOR ARRAY (EPA) With this method, the resolution of the EPA (Figure 10-8 on page 10-18 and Figure 10-9 on page 10-19) determines the maximum PWM output frequency. (Resolution is the minimum time re- quired between a capture or compare.) At 16 MHz, a 250 ns resolution results in a maximum PWM of 4 MHz.
Page 237 8XC196K x , J x , CA USER’S MANUAL Address: 1F98H T1CONTROL Reset State: The timer 1 control (T1CONTROL) register determines the clock source, counting direction, and count rate for timer 1. Function Number Mnemonic Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
Page 238 EVENT PROCESSOR ARRAY (EPA) Address: 1F9CH T2CONTROL Reset State: The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count rate for timer 2. Function Number Mnemonic Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
Page 239: Programming The Capture/Compare Channels
8XC196K x , J x , CA USER’S MANUAL 10.5.3 Programming the Capture/Compare Channels The EPAx_CON register controls the function of its assigned capture/compare channel. The reg- isters for EPA0, EPA2, and EPA4–9 are identical. The registers for EPA1 and EPA3 have an ad- ditional bit, the remap bit (RM), which is used to enable and disable remapping for high-speed PWM generation (see “Generating a High-speed PWM Output”...
Page 240 EVENT PROCESSOR ARRAY (EPA) Address: 1F60H + ( x * 4) EPA x _CON F700H ( x = 1 & 3) Reset State: x = 0–9 (8XC196K x ) 00H( x = 0, 2, 4–9) x = 0–3, 8, 9 (8XC196CA, J x ) The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels.
Page 241 8XC196K x , J x , CA USER’S MANUAL Address: 1F60H + ( x * 4) EPA x _CON (Continued) Reset State: F700H ( x = 1 & 3) x = 0–9 (8XC196K x ) 00H( x = 0, 2, 4–9) x = 0–3, 8, 9 (8XC196CA, J x ) The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels.
Page 242 EVENT PROCESSOR ARRAY (EPA) Address: 1F60H + ( x * 4) EPA x _CON (Continued) Reset State: F700H ( x = 1 & 3) x = 0–9 (8XC196K x ) 00H( x = 0, 2, 4–9) x = 0–3, 8, 9 (8XC196CA, J x ) The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels.
Page 243 8XC196K x , J x , CA USER’S MANUAL Address: 1F60H + ( x * 4) EPA x _CON (Continued) Reset State: F700H ( x = 1 & 3) x = 0–9 (8XC196K x ) 00H( x = 0, 2, 4–9) x = 0–3, 8, 9 (8XC196CA, J x ) The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels.
Page 244: Programming The Compare-Only Channels
EVENT PROCESSOR ARRAY (EPA) 10.5.4 Programming the Compare-only Channels To program a compare event, you must first write to the COMPx_CON (Figure 10-11) register to configure the compare-only channel and then load the event time into COMPx_TIME. COMPx_CON has the same bits and settings as EPAx_CON. COMPx_TIME is functionally iden- tical to EPAx_TIME.
Page 245: Enabling The Epa Interrupts
8XC196K x , J x , CA USER’S MANUAL Address: x = 0, 1F88H COMP x _CON x = 1, 1F8CH (Continued) Reset State: x = 0–1 The EPA compare control (COMP x _CON) registers determine the function of the EPA compare channels.
Page 246 EVENT PROCESSOR ARRAY (EPA) Address: 1FA0H EPA_MASK Reset State: 0000H The EPA interrupt mask (EPA_MASK) register enables or disables (masks) interrupts associated with the multiplexed EPA x interrupt. CA, Jx — — — — EPA8 EPA9 OVR0 OVR1 0VR2 OVR3 —...
Page 247: Determining Event Status
8XC196K x , J x , CA USER’S MANUAL 10.7 DETERMINING EVENT STATUS In compare mode, an interrupt pending bit is set each time a match occurs on an enabled event (even if the interrupt is specifically masked in the mask register). In capture mode, an interrupt pending bit is set each time a programmed event is captured and the event time moves from the capture buffer to the EPAx_TIME register.
Page 248: Servicing The Multiplexed Epa Interrupt With Software
EVENT PROCESSOR ARRAY (EPA) Address: 1FA6H EPA_PEND1 Reset State: When hardware detects a pending EPA x interrupt, it sets the corresponding bit in EPA interrupt pending (EPA_PEND or EPA_PEND1) registers. The EPAIPV register contains a number that identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA interrupt pending bit associated with the EPAIPV priority value is cleared.
Page 249 8XC196K x , J x , CA USER’S MANUAL Address: 1FA8H EPAIPV Reset State: When an EPA x interrupt occurs, the EPA interrupt priority vector register (EPAIPV) contains a number that identifies the highest priority, active, multiplexed interrupt source (see Table 10-7). EPAIPV allows software to branch via the TIJMP instruction to the correct interrupt service routine when EPA x is activated.
Page 250: Using The Tijmp Instruction To Reduce Interrupt Service Overhead
EVENT PROCESSOR ARRAY (EPA) 10.8.1 Using the TIJMP Instruction to Reduce Interrupt Service Overhead The EPAIPV register and the TIJMP instruction can be used together to reduce the interrupt ser- vice overhead. The primary purpose of the TIJMP instruction is to reduce the interrupt response time associated with servicing multiplexed interrupts.
Page 251 8XC196K x , J x , CA USER’S MANUAL INIT_INTERRUPTS: JTBASE_PTR,#LSW JTBASE ;store jump table base address EPAx_ISR: EPAIPV_PTR,#EPAIPV ;read EPAIPV offset PUSHA ;save INT_MASK/INT_MASK1/WSR/PSW TIJMP JTBASE_PTR,[EPAIPV_PTR],#1FH ;initiate jump to correct ISR OVR_EPA0_ISR: ;EPA0 overrun routine TIJMP JTBASE_PTR,[EPAIPV_PTR],#1FH ;check for pending ;interrupts, exit EPAx_DONE: POPA...
Page 252: Programming Examples For Epa Channels
Intel Literature Fulfillment or the Intel Applications Bulletin Board system (BBS). See Chapter 1, “Guide to This Manual,” for information about ordering information from Intel Literature and downloading files from the BBS. These sample program were written in the C programming lan- guage.
Page 253: Epa Capture Event Program
8XC196K x , J x , CA USER’S MANUAL void poll_epa0() if(checkbit(int_pend, EPA0_INT_BIT)) User code for event channel 0 would go here. */ Since this event is absolute and re-enabled, no polling is neccessary.*/ clrbit(int_pend, EPA0_INT_BIT); void main(void) /* Initialize the timers before using the epa */ init_timer1();...
Page 254: Epa Pwm Output Program
EVENT PROCESSOR ARRAY (EPA) time_value = epa0_time; /* must read to prevent overrun */ /* To generate have code for the epax interrupt,select the ICU design screen.*/ void init_timer1() t1control = COUNT_ENABLE | COUNT_UP | CLOCK_INTERNAL | DIVIDE_BY_1; void main(void) unsigned int time_value;...
Page 255 8XC196K x , J x , CA USER’S MANUAL /* Sample PTS control block initialization sequence.*/ void Init_PWM_toggle_PTS3(void) disable(); /* disable all interrupts */ disable_pts(); /* disable the PTS interrupts */ PWM_toggle_CB_3.constant2 = 127; PWM_toggle_CB_3.constant1 = 127; PWM_toggle_CB_3.pts_ptr = (void *)&EPA0_TIME; PWM_toggle_CB_3.ptscon = 0x42;...
Page 256: Analog-To-Digital Converter
Analog-to-digital Converter...
Page 258: A/D Converter Functional Overview
CHAPTER 11 ANALOG-TO-DIGITAL CONVERTER The analog-to-digital (A/D) converter can convert an analog input voltage to a digital value and set the A/D interrupt pending bit when it stores the result. It can also monitor a pin and set the A/D interrupt pending bit when the input voltage crosses over or under a programmed threshold voltage.
Page 259: A/D Converter Signals And Registers
8XC196K x , J x , CA USER’S MANUAL 11.2 A/D CONVERTER SIGNALS AND REGISTERS Table 11-1 lists the A/D signals and Table 11-2 describes the control and status registers. Al- though the analog inputs are multiplexed with I/O port pins, no configuration is necessary. Table 11-1.
Page 260: A/D Converter Operation
ANALOG-TO-DIGITAL CONVERTER Table 11-2. A/D Control and Status Registers (Continued) Mnemonic Address Description P0_PIN 1FDAH Port 0 Pin State Read P0_PIN to determine the current values of the port 0 pins. Reading the port induces noise into the A/D converter, decreasing the accuracy of any conversion in progress.
Page 261: Programming The A/D Converter
8XC196K x , J x , CA USER’S MANUAL The A/D converter uses a successive approximation algorithm to perform the analog-to-digital conversion. The converter hardware consists of a 256-resistor ladder, a comparator, coupling ca- pacitors, and a 10-bit successive approximation register (SAR) with logic that guides the process. The resistive ladder provides 20 mV steps (V = 5.12 volts), while capacitive coupling creates 5 mV steps within the 20 mV ladder voltages.
Page 262: Programming The A/D Test Register
ANALOG-TO-DIGITAL CONVERTER 11.4.1 Programming the A/D Test Register The AD_TEST register (Figure 11-2) selects either an analog input or a test voltage (ANGND or ) for conversion and specifies an offset voltage to be applied to the resistor ladder. To use the zero-offset adjustment, first perform two conversions, one on ANGND and one on V .
Page 263: Programming The A/D Result Register (For Threshold Detection Only)
8XC196K x , J x , CA USER’S MANUAL 11.4.2 Programming the A/D Result Register (for Threshold Detection Only) To use the threshold-detection modes, you must first write a value to the high byte of AD_RESULT to set the desired reference (threshold) voltage. Address: 1FAAH AD_RESULT (Write)
Page 264 ANALOG-TO-DIGITAL CONVERTER The AD_TIME register (Figure 11-4) specifies the A/D sample and conversion times. To avoid erroneous conversion results, use the T and T specifications on the datasheet to determine CONV appropriate values. Address: 1FAFH AD_TIME Reset State: The A/D time (AD_TIME) register programs the sample window time and the conversion time for each bit.
Page 265: Programming The A/D Command Register
8XC196K x , J x , CA USER’S MANUAL 11.4.4 Programming the A/D Command Register The A/D command register controls the operating mode, the analog input channel, and the con- version trigger. Address: 1FACH AD_COMMAND Reset State: The A/D command (AD_COMMAND) register selects the A/D channel number to be converted, controls whether the A/D converter starts immediately or with an EPA command, and selects the conversion mode.
Page 266: Enabling The A/D Interrupt
ANALOG-TO-DIGITAL CONVERTER 11.4.5 Enabling the A/D Interrupt The A/D converter can set the A/D interrupt pending bit when it completes a conversion or when the input voltage crosses the threshold value in the selected direction. To enable the interrupt, set the corresponding mask bit in the interrupt mask register (see Table 11-2 on page 11-2) and exe- cute the EI instruction to globally enable servicing of interrupts.
Page 267: Design Considerations
8XC196K x , J x , CA USER’S MANUAL Address: 1FAAH AD_RESULT (Read) Reset State: 7F80H The A/D result (AD_RESULT) register consists of two bytes. The high byte contains the eight most- significant bits from the A/D converter. The low byte contains the two least-significant bits from a ten- bit A/D conversion, indicates the A/D channel number that was used for the conversion, and indicates whether a conversion is currently in progress.
Page 268: Designing External Interface Circuitry
ANALOG-TO-DIGITAL CONVERTER 11.6.1 Designing External Interface Circuitry The external interface circuitry to an analog input is highly dependent upon the application and can affect the converter characteristics. Factors such as input pin leakage, sample capacitor size, and multiplexer series resistance from the input pin to the sample capacitor must be considered in the external circuit’s design.
Page 269: Minimizing The Effect Of High Input Source Resistance
8XC196K x , J x , CA USER’S MANUAL 11.6.1.1 Minimizing the Effect of High Input Source Resistance Under some conditions, the input source resistance (R ) can be great enough to affect the SOURCE measurement. You can minimize this effect by increasing the sample time or by connecting an external capacitor (C ) from the input pin to ANGND.
Page 270: Suggested A/D Input Circuit
ANALOG-TO-DIGITAL CONVERTER 11.6.1.2 Suggested A/D Input Circuit The suggested A/D input circuit shown in Figure 11-8 provides limited protection against over- voltage conditions on the analog input. Should the input voltage be driven significantly below ANGND or above V , diode D2 or D1 will forward bias at about 0.8 volts. The device’s input protection begins to turn on at approximately 0.5 volts beyond ANGND or V .
Page 271: Using Mixed Analog And Digital Inputs
8XC196K x , J x , CA USER’S MANUAL ANGND should be within about ± 50 mV of V should be well regulated and used only for the A/D converter. The V supply can be between 4.5 and 5.5 V and must be able to source approximately 5 mA (see the datasheet for actual specifications).
Page 272 ANALOG-TO-DIGITAL CONVERTER In many applications, it is less critical to record the absolute accuracy of an input than it is to de- tect that a change has occurred. This approach is acceptable as long as the converter is monotonic and has no missing codes. That is, increasing input voltages produce adjacent, unique output codes that are also increasing.
Page 273 8XC196K x , J x , CA USER’S MANUAL FINAL CODE TRANSITION OCCURS WHEN THE APPLIED VOLTAGE IS EQUAL TO (Vref – 1.5 (LSB)). ACTUAL CHARACTERISTIC OF AN IDEAL A/D CONVERTER THE VOLTAGE CHANGE BETWEEN THE ADJACENT CODE TRANSITIONS (THE “CODE WIDTH”) IS = 1 LSB.
Page 274 ANALOG-TO-DIGITAL CONVERTER FULL SCALE ERROR IDEAL CHARACTERISTIC ABSOLUTE ERROR ACTUAL CHARACTERISTIC ZERO OFFSET 6 1/2 INPUT VOLTAGE (LSBs) A0084-01 Figure 11-10. Actual and Ideal A/D Conversion Characteristics The actual characteristic of a hypothetical 3-bit converter is not perfect. When the ideal charac- teristic is overlaid with the actual characteristic, the actual converter is seen to exhibit errors in the locations of the first and final code transitions and in code widths, as shown in Figure 11-10.
Page 275 8XC196K x , J x , CA USER’S MANUAL Differential nonlinearity is the degree to which actual code widths differ from the ideal one-LSB width. It provides a measure of how much the input voltage may have changed in order to produce a one-count change in the conversion result.
Page 276 ANALOG-TO-DIGITAL CONVERTER IDEAL FULL-SCALE CODE TRANSITION IDEAL STRAIGHT LINE TRANSFER FUNCTION ACTUAL FULL-SCALE CODE TRANSITION DIFFERENTIAL TERMINAL BASED NON-LINEARITY CHARACTERISTIC (POSITIVE) (corrected for zero-offset and full-scale error) IDEAL CODE WIDTH ACTUAL CHARACTERISTIC NON-LINEARITY DIFFERENTIAL NON-LINEARITY (NEGATIVE) IDEAL CODE WIDTH ACTUAL FIRST TRANSITION IDEAL FIRST TRANSITION 6 1/2 INPUT VOLTAGE (LSBs)
Page 278: Can Serial Communications Controller
CAN Serial Communications Controller...
Page 279 <PageNum>-22...
Page 280: Can Functional Overview
The 87C196CA has a peripheral not found in the 8XC196Kx and 8XC196Jx controllers — the CAN (controller area network) peripheral. The CAN serial communications controller manages communications between multiple network nodes. This integrated peripheral is similar to Intel’s standalone 82527 CAN serial communications controller. It supports both the standard and the extended message frames specified by CAN 2.0 protocol parts A and B developed by Robert...
Page 281 8XC196K x , J x , CA USER’S MANUAL This bus configuration reduces point-to-point wiring requirements, making the CAN controller well suited to automotive and factory automation applications. In addition, it relieves the CPU of much of the communications burden while providing a high level of data integrity through error management logic.
Page 282: Can Controller Signals And Registers
CAN SERIAL COMMUNICATIONS CONTROLLER 12.2 CAN CONTROLLER SIGNALS AND REGISTERS Table 12-1 describes the CAN controller’s pins, and Table 12-2 describes the control and status registers. Table 12-1. CAN Controller Signals Signal Type Description RXCAN Receive This signal carries messages from other nodes on the CAN bus to the CAN controller. TXCAN Transmit This signal carries messages from the CAN controller to other nodes on the CAN bus.
Page 283: Can Controller Operation
8XC196K x , J x , CA USER’S MANUAL Table 12-2. Control and Status Registers (Continued) Register Register Description †† †† Mnemonic Address CAN_MSG x CON1 1E y 1H Message Object x Control 1 Program this register to indicate that a message is ready to transmit or to initiate a transmission.
Page 284: Address Map
CAN SERIAL COMMUNICATIONS CONTROLLER 12.3.1 Address Map The CAN controller has 256 bytes of RAM, containing 15 message objects and control and status registers at fixed addresses. Each message object occupies 15 consecutive bytes beginning at a base address that is a multiple of 16 bytes. The byte above each message object is reserved (indi- cated by a dash (—) ) or occupied by a control register.
Page 285: Receive And Transmit Priorities
8XC196K x , J x , CA USER’S MANUAL Table 12-4. Message Object Structure † Hex Address Contents 1E x 7–1E x E Data Bytes 0–7 1E x 6 Message Configuration 1E x 2–1E x 5 Message Identifier 0–3 1E x 0–1E x 1 Message Control 0–1 †...
Page 286: Message Frames
CAN SERIAL COMMUNICATIONS CONTROLLER Table 12-5. Effect of Masking on Message Identifiers Transmit message object ID 1 1 0 0 0 0 0 0 0 0 0 Mask (0 = don’t care; 1 = must match) 0 0 0 0 0 0 0 0 0 1 1 Received remote message object ID 0 0 1 1 1 1 1 1 1 0 0 Resulting message object ID...
Page 287 8XC196K x , J x , CA USER’S MANUAL Table 12-6. Standard Message Frame Field Description Bit Count Start-of-frame. A dominant (0) bit marks the beginning of a message frame. 11-bit message identifier. Arbitration RTR. Remote transmission request. Dominant (0) for data frames; recessive (1) for remote frames.
Page 288: Error Detection And Management Logic
CAN SERIAL COMMUNICATIONS CONTROLLER 12.3.4 Error Detection and Management Logic The CAN controller has several error detection mechanisms, including cyclical redundancy checking (CRC) and bit coding rules (stuffing and destuffing). The CAN controller generates a CRC code for transmitted messages and checks the CRC code of incoming messages. The CRC polynomial has been optimized for control applications with short messages.
Page 289: Bit Timing
8XC196K x , J x , CA USER’S MANUAL 12.3.5 Bit Timing A message object consists of a series of bits transmitted in consecutive bit times. The CAN pro- tocol specifies a bit time composed of four separate, nonoverlapping time segments: a synchro- nization delay segment, a propagation delay segment, and two phase delay segments (Figure 12-4 and Table 12-8).
Page 290 CAN SERIAL COMMUNICATIONS CONTROLLER Bit Time SYNC TSEG1 TSEG2 _SEG 1 tq (TSEG1 + 1)tq (TSEG2 + 1)tq Sample Transmit A2602-01 Figure 12-5. A Bit Time as Implemented in the CAN Controller Table 12-9. CAN Controller Bit Time Segments Symbol Definition This time segment is equivalent to SYNC_SEG in the CAN protocol.
Page 291: Bit Timing Equations
8XC196K x , J x , CA USER’S MANUAL 12.3.5.1 Bit Timing Equations The bit timing equations of the integrated CAN controller are equivalent to those for the 82527 CAN peripheral with the DSC bit in the CPU interface register set (system clock divided by two). The following equations show the timing calculations for the integrated CAN controller and the 82527 CAN peripheral, respectively.
Page 292: Configuring The Can Controller
CAN SERIAL COMMUNICATIONS CONTROLLER 12.4 CONFIGURING THE CAN CONTROLLER This section explains how to configure the CAN controller. Several registers combine to control the configuration: the CAN control register, the two bit timing registers, and the three mask reg- isters. 12.4.1 Programming the CAN Control (CAN_CON) Register The CAN control register (Figure 12-6) controls write access to the bit timing registers, enables and disables global interrupt sources (error, status change, and individual message object), and...
Page 293 8XC196K x , J x , CA USER’S MANUAL Address: 1E00H CAN_CON (Continued) Reset State: (87C196CA) Program the CAN control (CAN_CON) register to control write access to the bit timing registers, to enable and disable CAN interrupts, and to control access to the CAN bus. 87C196CA —...
Page 294: Programming The Bit Timing 0 (Can_Btime0) Register
CAN SERIAL COMMUNICATIONS CONTROLLER 12.4.2 Programming the Bit Timing 0 (CAN_BTIME0) Register Bit timing register 0 (Figure 12-7) defines the length of one time quantum and the maximum amount by which the sample point can be moved (t or t can be shortened and the other TSEG TSEG...
Page 295: Programming The Bit Timing 1 (Can_Btime1) Register
8XC196K x , J x , CA USER’S MANUAL 12.4.3 Programming the Bit Timing 1 (CAN_BTIME1) Register Bit timing register 1 (Figure 12-8) controls the time at which the bus is sampled and the number of samples taken. In single-sample mode, the bus is sampled once and the value of that sample is considered valid.
Page 296 CAN SERIAL COMMUNICATIONS CONTROLLER Address: 1E4FH CAN_BTIME1 Reset State: Unchanged (87C196CA) Program the CAN bit timing 1 (CAN_BTIME1) register to define the sample time and the sample mode. The CAN controller samples the bus during the last one (in single-sample mode) or three (in three-sample mode) time quanta of t , and initiates a transmission at the end of t TSEG...
Page 297: Programming A Message Acceptance Filter
8XC196K x , J x , CA USER’S MANUAL 12.4.4 Programming a Message Acceptance Filter The mask registers provide a method for developing an acceptance filtering strategy. Without a filtering strategy, a message object could accept an incoming message only if their identifiers were identical.
Page 298 CAN SERIAL COMMUNICATIONS CONTROLLER CAN_EGMSK Address: 1E0BH, 1E0AH, 1E09H, 1E08H (87C196CA) Reset State: Unchanged Program the CAN extended global mask (CAN_EGMSK) register to mask (“don’t care”) specific message identifier bits for extended message objects. 87C196CA MSK4 MSK3 MSK2 MSK1 MSK0 —...
Page 299: Configuring Message Objects
8XC196K x , J x , CA USER’S MANUAL CAN_MSK15 Address: 1E0FH, 1E0EH, 1E0DH, 1E0CH (87C196CA) Reset State: Unchanged Program the CAN message 15 mask (CAN_MSK15) register to mask (“don’t care”) specific message identifier bits for message 15 in addition to those bits masked by a global mask (CAN_EGMSK or CAN_SGMSK).
Page 300: Specifying A Message Object's Configuration
CAN SERIAL COMMUNICATIONS CONTROLLER 12.5.1 Specifying a Message Object’s Configuration Each message object configuration register (Figure 12-12) specifies a message identifier type (standard or extended), transfer direction (transmit or receive), and data length (in bytes). CAN_MSG x CFG Address: 1E x 6H ( x = 1–F) Reset State: Unchanged x = 1–15 (87C196CA)
Page 301: Programming The Message Object Identifier
8XC196K x , J x , CA USER’S MANUAL 12.5.2 Programming the Message Object Identifier For messages with extended identifiers, write the identifier to bits ID28:0. For messages with standard identifiers, write the identifier to bits ID28:18. Software can change the identifier during normal operation without requiring a subsequent device reset.
Page 302: Programming The Message Object Control Registers
CAN SERIAL COMMUNICATIONS CONTROLLER 12.5.3 Programming the Message Object Control Registers Each message object control register consists of four bit pairs — one bit of each pair is in true form and one is in complement form. This format allows software to set or clear any bit with a single write operation, without affecting the remaining bits.
Page 303 8XC196K x , J x , CA USER’S MANUAL CAN_MSG x CON0 Address: 1E x 0H ( x = 1–F) Reset State: Unchanged x = 1–15 (87C196CA) Program the CAN message object x control 0 (CAN_MSG x CON0) register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt.
Page 304 CAN SERIAL COMMUNICATIONS CONTROLLER CAN_MSG x CON0 (Continued) Address: 1E x 0H ( x = 1–F) Reset State: Unchanged x = 1–15 (87C196CA) Program the CAN message object x control 0 (CAN_MSG x CON0) register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt.
Page 305 8XC196K x , J x , CA USER’S MANUAL CAN_MSG x CON1 Address: 1E x 1H ( x = 1–F) Reset State: Unchanged x = 1–15 (87C196CA) The CAN message object x control 1 (CAN_MSG x CON1) register indicates whether a message object has been updated, whether a message has been overwritten, whether the CPU is updating the message, and whether a transmission or reception is pending.
Page 306 CAN SERIAL COMMUNICATIONS CONTROLLER CAN_MSG x CON1 (Continued) Address: 1E x 1H ( x = 1–F) Reset State: Unchanged x = 1–15 (87C196CA) The CAN message object x control 1 (CAN_MSG x CON1) register indicates whether a message object has been updated, whether a message has been overwritten, whether the CPU is updating the message, and whether a transmission or reception is pending.
Page 307 8XC196K x , J x , CA USER’S MANUAL CAN_MSG x DATA0–7 Address: 1E x EH, 1E x DH, 1E x CH, 1E x BH, x = 1–15 (87C196CA) 1E x AH, 1E x 9H, 1E x 8H, 1E x 7H ( x = 1–F) Reset State: Unchanged...
Page 308: Enabling The Can Interrupts
CAN SERIAL COMMUNICATIONS CONTROLLER 12.6 ENABLING THE CAN INTERRUPTS The CAN controller has a single interrupt input (INT13) to the interrupt controller. (Generally, PTS interrupt service is not useful for the CAN controller because the PTS cannot readily deter- mine the source of the CAN controller’s multiplexed interrupts.) To enable the CAN controller’s interrupts, you must enable the interrupt source by setting the CAN bit in INT_MASK1 (see Ta- ble 12-2 on page 12-3) and globally enable interrupt servicing (by executing the EI instruction).
Page 309 8XC196K x , J x , CA USER’S MANUAL Address: 1E00H CAN_CON (Continued) Reset State: (87C196CA) Program the CAN control (CAN_CON) register to control write access to the bit timing registers, to enable and disable CAN interrupts, and to control access to the CAN bus. 87C196CA —...
Page 310 CAN SERIAL COMMUNICATIONS CONTROLLER CAN_MSG x CON0 Address: 1E x 0H ( x = 1–F) Reset State: Unchanged x = 1–15 (87C196CA) Program the CAN message object x control 0 (CAN_MSG x CON0) register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt.
Page 311: Determining The Can Controller's Interrupt Status
8XC196K x , J x , CA USER’S MANUAL 12.7 DETERMINING THE CAN CONTROLLER’S INTERRUPT STATUS A successful reception or transmission or a change in the status register can cause the CAN con- troller to generate an interrupt request. The INT_PEND1 register (see Table 12-2 on page 12-3) indicates whether a CAN interrupt request is pending.
Page 312 CAN SERIAL COMMUNICATIONS CONTROLLER If a status change generated the interrupt (CAN_INT = 01H), software can read the CAN status register (Figure 12-20) to determine the source of the interrupt request. Address: 1E01H CAN_STAT Reset State: (87C196CA) The CAN status (CAN_STAT) register reflects the current status of the CAN peripheral. 87C196CA BUSOFF WARN...
Page 313 8XC196K x , J x , CA USER’S MANUAL If an individual message object caused the interrupt request (CAN_INT = 02–10H), software can read the associated message object control 0 register (Figure 12-21). The INT_PND bit-pair will be set, indicating that a receive or transmit interrupt request is pending CAN_MSG x CON0 1E x 0H ( x =1–F) Address:...
Page 314: Flow Diagrams
CAN SERIAL COMMUNICATIONS CONTROLLER 12.8 FLOW DIAGRAMS The flow diagrams in this section describe the steps that your software (shown as CPU) and the CAN controller execute to receive and transmit messages. Table 12-13 lists the register bits shown in the diagrams along with their associated registers and a cross-reference to the figure that describes them.
Page 315 8XC196K x , J x , CA USER’S MANUAL Power Up (All bits undefined) MSGVAL := 1 INT_PND := 0 TXIE := (Application specific) RXIE := (Application specific) Initialization NEWDAT := 0 RMTPND := 0 TX_REQ := 0 MSGLST := 0 := (don't care) := 0 (receive) := (Application specific)
Page 316 CAN SERIAL COMMUNICATIONS CONTROLLER (All bits undefined) Power Up MSGVAL := 1 INT_PND := 0 RXIE := (Application specific) Initialization NEWDAT := 0 RMTPND := 0 MSGLST := 0 := 0 (receive) := (Application specific) := (Application specific) MASK := (Application specific) Process message contents.
Page 317 8XC196K x , J x , CA USER’S MANUAL Bus idle? TX_REQ=1? Received frame with MSGLST=0? same identifer as this message object? NEWDAT := 0 Load identifer and control into buffer NEWDAT = 1? Send remote frame MSGLST := 1 Transmission Store message successful?
Page 318 CAN SERIAL COMMUNICATIONS CONTROLLER (All bits undefined) Power Up MSGVAL := 1 INT_PND := 0 TXIE := (Application specific) RXIE := (Application specific) Initialization NEWDAT := 0 RMTPND := 0 TX_REQ := 0 MSGLST := 0 := (Application specific) := 1 (transmit) := (Application specific) := (Application specific) CPUUPD := 1...
Page 319 8XC196K x , J x , CA USER’S MANUAL Bus free? TX_REQ= 1? Received remote frame CPUUPD= 0? with same identifer as this message object? NEWDAT := 0 Load message into buffer TX_REQ := 1 RMTPND := 1 Send message RXIE = 1 Transmission successful?
Page 320: Design Considerations
CAN SERIAL COMMUNICATIONS CONTROLLER 12.9 DESIGN CONSIDERATIONS This section outlines design considerations for the CAN controller. 12.9.1 Hardware Reset A hardware reset clears the error management counters and the bus-off state and leaves the reg- isters with the values listed in Table 12-14. Table 12-14.
Page 321 8XC196K x , J x , CA USER’S MANUAL The CAN controller synchronizes itself to the CAN bus by waiting for 128 bus idle states (128 occurrences of 11 consecutive recessive bits) before participating in bus activities. During this se- quence, the CAN controller writes a bit 0 error code to the LEC2:0 bits of the status register each time it receives a recessive bit.
Page 322: Minimum Hardware Considerations
Minimum Hardware Considerations...
Page 324: Minimum Connections
CHAPTER 13 MINIMUM HARDWARE CONSIDERATIONS The 8XC196Kx, Jx, and CA have several basic requirements for operation within a system. This chapter describes options for providing the basic requirements and discusses other hardware con- siderations. 13.1 MINIMUM CONNECTIONS Table 13-1 lists the signals that are required for the device to function and Figure 13-1 shows the connections for a minimum configuration.
Page 325: Unused Inputs
8XC196K x , J x , CA USER’S MANUAL Table 13-1. Minimum Required Signals(Continued) Signal Type Description Name XTAL1 Input Crystal/Resonator or External Clock Input Input to the on-chip oscillator and the internal clock generators. The internal clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When using an external clock source instead of the on-chip oscillator, connect the clock input to XTAL1.
Page 326 MINIMUM HARDWARE CONSIDERATIONS (Note 1) 20 pF 20 pF XTAL2 XTAL1 RESET# (Note 2) 0.01 µF 4.7 µF BUSWIDTH (Note 3) READY 1 µF 1 µF BHE# ANGND Port 5 / Bus Control (Note 4) Input-only INST Port Pins (Note 5) 8XC196 Device Notes: 1.
Page 327: Applying And Removing Power
8XC196K x , J x , CA USER’S MANUAL 13.2 APPLYING AND REMOVING POWER When power is first applied to the device, RESET# must remain continuously low for at least one state time after the power supply is within tolerance and the oscillator/clock has stabilized; oth- erwise, operation might be unpredictable.
Page 328: Providing The Clock
MINIMUM HARDWARE CONSIDERATIONS If the A/D converter will be used, connect V to a separate reference supply to minimize noise during A/D conversions. Even if the A/D converter will not be used, V and ANGND must be connected to provide power to port 0. Refer to “Analog Ground and Reference Voltages” on page 11-13 for a detailed discussion of A/D power and ground recommendations.
Page 329 8XC196K x , J x , CA USER’S MANUAL To internal circuitry V CC XTAL2 XTAL1 (Output) (Input) Oscillator Enable# (from powerdown circuitry) V SS A0076-03 Figure 13-3. On-chip Oscillator Circuit Figure 13-4 shows the connections between the external crystal and the device. When designing an external oscillator circuit, consider the effects of parasitic board capacitance, extended oper- ating temperatures, and crystal specifications.
Page 330: Using A Ceramic Resonator Instead Of A Crystal Oscillator
MINIMUM HARDWARE CONSIDERATIONS XTAL1 XTAL1 8XC196 8XC196 Device Device XTAL2 XTAL2 Quartz Crystal Quartz Crystal Note: Note: Mount oscillator components close to the device and use Mount oscillator components close to the device and use short, direct traces to XTAL1, XTAL2, and V ss . When short, direct traces to XTAL1, XTAL2, and V ss .
Page 331: Resetting The Device
8XC196K x , J x , CA USER’S MANUAL V CC V CC 4.7 kΩ † 4.7 kΩ † External External XTAL1 XTAL1 Clock Input Clock Input 8XC196 Device 8XC196 Device Clock Driver Clock Driver No Connection No Connection XTAL2 XTAL2 †...
Page 332 MINIMUM HARDWARE CONSIDERATIONS Figure 13-7 shows the reset-sequence timing. Depending upon when RESET# is brought high, the CLKOUT signal may become out of phase with the PH1 internal clock. When this occurs, the clock generator immediately resynchronizes CLKOUT as shown in Case 2. Internal Internal Reset...
Page 333: Generating An External Reset
8XC196K x , J x , CA USER’S MANUAL Internal External V CC Clock Reset State Machine Internal † R RST Reset Trigger Signal Count Complete RESET# ~200 Ω RST Instruction WDT Overflow IDLPD Invalid Key USFR.0 (F OSC < 100 kHz) †...
Page 334 MINIMUM HARDWARE CONSIDERATIONS RESET# RESET# 4.7 µF 4.7 µF 8XC196 Device 8XC196 Device A0276-01 A0276-01 Figure 13-9. Minimum Reset Circuit The other devices may not be reset because the capacitor will keep the voltage above V . Since RESET# is asserted for only 16 state times, it may be necessary to lengthen and buffer the system- reset pulse.
Page 335: Issuing The Reset (Rst) Instruction
8XC196K x , J x , CA USER’S MANUAL 13.5.2 Issuing the Reset (RST) Instruction The RST instruction (opcode FFH) resets the device by pulling RESET# low for 16 state times. It also clears the processor status word (PSW), sets the master program counter (PC) to 2080H, and resets the special function registers (SFRs).
Page 336: Special Operating Modes
Special Operating Modes...
Page 338: Special Operating Mode Signals And Registers
CHAPTER 14 SPECIAL OPERATING MODES The 8XC196Kx, Jx, and CA have two power saving modes: idle and powerdown. They also pro- vide an on-circuit emulation (ONCE) mode that electrically isolates the device from the other sys- tem components. This chapter describes each mode and explains how to enter and exit each. (Refer to Appendix A for descriptions of the instructions discussed in this chapter, to Appendix B for descriptions of signal status during each mode, and to Appendix C for details about the reg- isters.)
Page 339 8XC196K x , J x , CA USER’S MANUAL Table 14-1. Operating Mode Control Signals (Continued) Signal Port Pin Type Description Name P5.4 Test- Test-mode entry (CA, KT, mode If this pin is held low during reset, the device will enter a reserved test entry mode, so exercise caution if you use this pin for input.
Page 340: Reducing Power Consumption
SPECIAL OPERATING MODES 14.2 REDUCING POWER CONSUMPTION Both power-saving modes conserve power by disabling portions of the internal clock circuitry (Figure 14-1). The following paragraphs describe both modes in detail. Disable Clock Input (Powerdown) Divide-by-two XTAL1 Circuit Disable Clocks (Powerdown) XTAL2 Peripheral Clocks (PH1, PH2) Clock...
Page 341: Powerdown Mode
8XC196K x , J x , CA USER’S MANUAL The device enters idle mode after executing the IDLPD #1 instruction. Either an interrupt or a hardware reset will cause the device to exit idle mode. Any enabled interrupt source, either inter- nal or external, can cause the device to exit idle mode.
Page 342: Entering Powerdown Mode
SPECIAL OPERATING MODES 14.4.2 Entering Powerdown Mode Before entering powerdown, complete the following tasks: • Complete all serial port transmissions or receptions. Otherwise, when the device exits powerdown, the serial port activity will continue where it left off and incorrect data may be transmitted or received.
Page 343: Generating A Hardware Reset
8XC196K x , J x , CA USER’S MANUAL 14.4.3.2 Generating a Hardware Reset The device will exit powerdown if RESET# is asserted. If the design uses an external clock input signal rather than the on-chip oscillator, RESET# must remain low for at least 16 state times. If the design uses the on-chip oscillator, then RESET# must be held low until the oscillator has sta- bilized.
Page 344 SPECIAL OPERATING MODES When using an external interrupt signal to exit powerdown mode, we recommend that you con- nect the external RC circuit shown in Figure 14-3 to the V pin. The discharging of the capacitor causes a delay that allows the oscillator to stabilize before the internal CPU and peripheral clocks are enabled.
Page 345 8XC196K x , J x , CA USER’S MANUAL EXTINT 200 µA C 1 Discharge R 1 x C 1 Recovery V PP , Volts Time Constant Pullup On Code Execution Resumes Time, ms A0151-01 Figure 14-4. Typical Voltage on the V Pin While Exiting Powerdown Select a resistor that will not interfere with the discharge current.
Page 346: Once Mode
SPECIAL OPERATING MODES For example, assume that the oscillator needs at least 12.5 ms to discharge (T = 12.5 ms), V is 2.5 V, and the discharge current is 200 µA. The minimum C capacitor size is 1 µF. × 0.0125 0.0002 1 µF ------------------------------------------ -...
Page 347: Reserved Test Modes
8XC196K x , J x , CA USER’S MANUAL 14.6 RESERVED TEST MODES A special test-mode-entry pin (Table 14-4) is provided for Intel’s in-house testing only. These test modes can be entered accidentally if you configure the test-mode-entry pin as an input and hold it low during the rising edge of RESET#.
Page 348: Interfacing With External Memory
Interfacing with External Memory...
Page 350: External Memory Interface Signals
CHAPTER 15 INTERFACING WITH EXTERNAL MEMORY The device can interface with a variety of external memory devices. It supports either a fixed 8- bit bus width, a fixed 16-bit bus width, or a dynamic 8-bit/16-bit bus width; internal control of wait states for slow external memory devices;...
Page 351 8XC196K x , J x , CA USER’S MANUAL Table 15-1. External Memory Interface Signals (Continued) Function Multiplexed Type Description Name With Address Latch Enable ADV#/P5.0 This active-high output signal is asserted only during external memory cycles. ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus.
Page 352 INTERFACING WITH EXTERNAL MEMORY Table 15-1. External Memory Interface Signals (Continued) Function Multiplexed Type Description Name With CLKOUT Clock Output P2.7 Output of the internal clock generator. The CLKOUT frequency is ½ the oscillator frequency input (XTAL1). CLKOUT has a 50% duty cycle.
Page 353: Chip Configuration Registers And Chip Configuration Bytes
8XC196K x , J x , CA USER’S MANUAL Table 15-1. External Memory Interface Signals (Continued) Function Multiplexed Type Description Name With † READY Ready Input P5.6 This active-high input signal is used to lengthen external memory cycles for slow memory by generating wait states in addition to the wait states that are generated internally.
Page 354 INTERFACING WITH EXTERNAL MEMORY Address: 2018H CCR0 Reset State: The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus width.
Page 355 8XC196K x , J x , CA USER’S MANUAL Address: 2018H CCR0 (Continued) Reset State: The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus width.
Page 356 INTERFACING WITH EXTERNAL MEMORY Address: 201AH CCR1 Reset State: The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width. CA, J x , KQ, KR IRC2 KS, KT...
Page 357: Bus Width And Multiplexing
8XC196K x , J x , CA USER’S MANUAL Address: 201AH CCR1 (Continued) Reset State: The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width. CA, J x , KQ, KR IRC2 KS, KT...
Page 358 INTERFACING WITH EXTERNAL MEMORY Bus Control Bus Control 8-bit Address 16-bit Multiplexed High Address/Data AD15:8 AD15:0 (Port 4) (Ports 4 and 3) 8-bit Multiplexed Address/Data AD7:0 (Port 3) 8XC196 8XC196 16-bit Bus 8-bit Bus A3068-01 Figure 15-3. Multiplexing and Bus Width Options After reset, but before the CCB fetch, the device is configured for 8-bit bus mode, regardless of the BUSWIDTH input.
Page 359: Timing Requirements For Buswidth
8XC196K x , J x , CA USER’S MANUAL XTAL1 CLKOUT (MIN) LLGV CLGX BUSWIDTH Valid AVGV Data Address A0164-02 Figure 15-4. BUSWIDTH Timing Diagram The BUSWIDTH signal can be used in numerous applications. For example, a system could store code in a 16-bit memory device and data in an 8-bit memory device.
Page 360: 16-Bit Bus Timings
INTERFACING WITH EXTERNAL MEMORY 15.3.2 16-bit Bus Timings When the device is configured to operate in the 16-bit bus-width mode, lines AD15:0 form a 16- bit multiplexed address/data bus. Figure 15-5 shows an idealized timing diagram for the external read and write cycles. (Comprehensive timing specifications are shown in Figure 15-24). The rising edge of the address latch enable (ALE) indicates that the device is driving an address onto the bus (AD15:0).
Page 361 8XC196K x , J x , CA USER’S MANUAL XTAL1 CLKOUT Valid BUSWIDTH Address Out Data In AD15:0 (Read) INST Valid Address Out Data Out AD15:0 (Write) A3074-01 Figure 15-5. Timings for 16-bit Buses 15-12...
Page 362: 8-Bit Bus Timings
INTERFACING WITH EXTERNAL MEMORY 15.3.3 8-bit Bus Timings When the device is configured to operate in the 8-bit bus mode, lines AD7:0 form a multiplexed lower address and data bus. Lines AD15:8 are not multiplexed; the upper address is latched and remains valid throughout the bus cycle.
Page 363: Wait States (Ready Control)
8XC196K x , J x , CA USER’S MANUAL XTAL1 CLKOUT BUSWIDTH Address Out Address Out AD15:8 Address Address Low data in High data in AD7:0 +1 Out (Read) INST Address Address AD7:0 Low data out High data out +1 Out (Write) A3075-01 Figure 15-6.
Page 364 INTERFACING WITH EXTERNAL MEMORY After reset and until CCB1 is read, the bus controller always inserts three wait states into bus cy- cles. Then, until P5.6 has been configured to operate as the READY signal, the internal ready control bits (IRC2:0) control the wait states. If IRC2:0 are all set during CCB0 and CCB1 fetch, READY (P5.6) is configured as a special-function input.
Page 365 8XC196K x , J x , CA USER’S MANUAL Table 15-2. READY Signal Timing Definitions Symbol Definition READY Hold after CLKOUT Low CLYX Minimum hold time is typically 0 ns. If maximum specification is exceeded, additional wait states will occur. Address Valid to READY Setup AVYV Maximum time the memory system has to assert READY after the device outputs the address...
Page 366: Bus-Hold Protocol (8Xc196Kq, Kr, Ks, Kt Only)
INTERFACING WITH EXTERNAL MEMORY 15.5 BUS-HOLD PROTOCOL (8XC196KQ, KR, KS, KT ONLY) The 8XC196Kx device supports a bus-hold protocol that allows external devices to gain control of the address/data bus. The protocol uses three signals, all of which are port 2 special functions: HOLD#/P2.5 (hold request), HLDA#/P2.6 (hold acknowledge), and BREQ#/P2.3 (bus request).
Page 367: Enabling The Bus-Hold Protocol (8Xc196K X Only)
8XC196K x , J x , CA USER’S MANUAL Table 15-3. HOLD#, HLDA# Timing Definitions Symbol Parameter HOLD# Setup Time HVCH CLKOUT Low to HLDA# Low CLHAL CLKOUT Low to HLDA# High CLHAH CLKOUT Low to BREQ# Low CLBRL CLKOUT Low to BREQ# High CLBRH HLDA# Low to Address Float HALAZ...
Page 368: Disabling The Bus-Hold Protocol (8Xc196K X Only)
INTERFACING WITH EXTERNAL MEMORY You must also set the hold enable bit (HLDEN) in the window selection register (WSR.7) to en- able the bus-hold protocol. Once the bus-hold protocol has been selected, the port functions of P2.3, P2.5, and P2.6 cannot be selected without resetting the device. (During the time that the pins are configured to operate as special-function signals, their special-function values can be read from the P2_PIN.x bits.) However, the hold function can be dynamically enabled and disabled as described in “Disabling the Bus-hold Protocol (8XC196Kx Only).”...
Page 369: Regaining Bus Control (8Xc196K X Only)
8XC196K x , J x , CA USER’S MANUAL 15.5.4 Regaining Bus Control (8XC196K x Only) While HOLD# is asserted, the device continues executing code until it needs to access the exter- nal bus. If executing from internal memory, it continues until it needs to perform an external memory cycle.
Page 370 INTERFACING WITH EXTERNAL MEMORY WR# or RD# WR# or RD# BHE# AD7:0 Valid Addr Low Data Out AD15:0 AD15:8 Address High Addr Data Out 16-bit Bus Cycle 8-bit Bus Cycle A3077-01 Figure 15-9. Standard Bus Control When the device is configured to use a 16-bit bus, separate low- and high-byte write signals must be generated for single-byte writes.
Page 371 8XC196K x , J x , CA USER’S MANUAL Figure 15-11 shows an 8-bit system with both flash and RAM. The flash is the lower half of mem- ory, and the RAM is the upper half. This system configuration uses the most-significant address bit (AD15) as the chip-select signal and ALE as the address-latch signal.
Page 372 INTERFACING WITH EXTERNAL MEMORY Figure 15-12 shows a system that uses the dynamic bus-width feature. (The CCR bits, BW0 and BW1, are set.) Code is executed from the two EPROMs and data is stored in the byte-wide RAM. The RAM is in high memory. It is selected by driving AD15 high, which also selects the 8-bit bus width mode by driving the BUSWIDTH signal low.
Page 373: Write Strobe Mode
8XC196K x , J x , CA USER’S MANUAL 15.6.2 Write Strobe Mode The write strobe mode eliminates the need to externally decode high- and low-byte writes to ex- ternal 16-bit RAM in 16-bit bus mode. When the write strobe mode is selected, the device gen- erates WRL# and WRH# instead of WR# and BHE#.
Page 374 INTERFACING WITH EXTERNAL MEMORY Figure 15-14 shows a 16-bit system with two EPROMs and two RAMs. It is configured to use the write strobe mode. ALE latches the address; AD15 is the chip-select signal for the EPROMs and RAMs. WRL# is asserted during low byte writes and word writes. WRH# is asserted during high byte writes and word writes.
Page 375: Address Valid Strobe Mode
8XC196K x , J x , CA USER’S MANUAL 15.6.3 Address Valid Strobe Mode When the address valid strobe mode is selected, the device generates the address valid signal (ADV#) instead of the address latch enable signal (ALE). ADV# is asserted after an external ad- dress is valid (see Figure 15-15).
Page 376 INTERFACING WITH EXTERNAL MEMORY Figure 15-17 and Figure 15-18 show sample circuits that use address valid strobe mode. Figure 15-17 shows a simple 8-bit system with a single flash. It is configured for the address valid strobe mode. This system configuration uses the ADV# signal as both the flash chip-select signal and the address-latch signal.
Page 377 8XC196K x , J x , CA USER’S MANUAL Figure 15-18 shows a 16-bit system with two EPROMs. This system configuration uses the ADV# signal as both the EPROM chip-select signal and the address-latch signal. BUSWIDTH A14:8 A15:8 74AC AD15:8 A13:7 A13:7 D15:8...
Page 378: Address Valid With Write Strobe Mode
INTERFACING WITH EXTERNAL MEMORY 15.6.4 Address Valid with Write Strobe Mode When the address valid with write strobe mode is selected, the device generates the ADV#, WRL#, and WRH# bus-control signals. This mode is used for a simple system using external 16- bit RAM.
Page 379: Bus Timing Modes (8Xc196Ks, Kt Only)
8XC196K x , J x , CA USER’S MANUAL V CC BUSWIDTH A13:8 74AC AD15:8 A12:7 A12:7 D15:8 ADV# D7:0 8K×8 8K×8 8XC196 (High) (Low) A7:1 74AC AD7:0 A6:0 A6:0 WRH# WRL# A3097-01 Figure 15-20. 16-bit System with RAM 15.7 BUS TIMING MODES (8XC196KS, KT ONLY) The 8XC196KS, KT devices have selectable bus timing modes controlled by the MSEL0 and MSEL1 bits (bits 6 and 7) of CCR1.
Page 380 INTERFACING WITH EXTERNAL MEMORY MODE 3 CLKOUT = 1 T = 1 T T RHDZ RLDV DATA ADDR DATA ADDR DATA ADDR = 3 T AVDV MODE 0 = 3 T RLDV = 1 T RHDZ DATA ADDR DATA ADDR DATA = 5 T AVDV...
Page 381: Mode 3, Standard Mode
8XC196K x , J x , CA USER’S MANUAL Table 15-6. Modes 0, 1, 2, and 3 Timing Comparisons Timing Specifications (in T ) Note 1 Mode CLLH CHLH AVLL AVDV RLRH RHDZ RLDV Mode 3 Mode 0 Mode 1 Mode 2 NOTES: These are ideal timing values for purposes of comparison only.
Page 382: Mode 2, Long Read/Write With Early Address
INTERFACING WITH EXTERNAL MEMORY XTAL 1 XHCH CHCL CLCL CLKOUT CLLL CHLH LHLH ALE/ADV# LHLL LLRL RHLH RLRH RLDV RLAZ AVLL LLAX RHDZ Bus Read Address Data In D15:0 AD15:0 8- and16-bit AVDV Bus Mode LLWL WLWH QVWH WHQX Bus Write Address Out Data Out AD15:0...
Page 383: Design Considerations
8XC196K x , J x , CA USER’S MANUAL 15.7.5 Design Considerations In all bus timing modes, for 16-bit bus-width operation, latch the upper and lower address/data lines. In modes 1 and 2, for 8-bit bus-width operation, also latch the upper and lower address/data lines;...
Page 384 INTERFACING WITH EXTERNAL MEMORY XTAL 1 XHCH CHCL CLCL CLKOUT CLLL CHLH LHLH ALE/ADV# LHLL LLRL RHLH RLRH RLDV RLAZ RHDZ AVLL LLAX Bus Read Address Data In D15:0 AD15:0 8- and 16-bit AVDV Bus Mode LLWL WLWH QVWH WHQX Bus Write Address Out Data Out...
Page 385: System Bus Ac Timing Specifications
8XC196K x , J x , CA USER’S MANUAL 15.8 SYSTEM BUS AC TIMING SPECIFICATIONS Refer to the latest data sheet for the AC timings to make sure your system meets specifications. The major external bus timing specifications are shown in Figure 15-24. XTAL1 CLCL CHCL...
Page 386 INTERFACING WITH EXTERNAL MEMORY Each symbol consists of two pairs of letters prefixed by “T” (for time). The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two sig- nal/condition points. For example, is the time between signal C (CLKOUT) condition L CLDV (Low) and signal D (Input Data) condition V (Valid).
Page 387 8XC196K x , J x , CA USER’S MANUAL Table 15-8. AC Timing Definitions (Continued) Symbol Definition The External Memory System Must Meet These Specifications (Continued) † ALE Low to BUSWIDTH Valid LLGV Maximum time after ALE/ADV# falls until BUSWIDTH must be valid. If this specification is exceeded, the 8XC196K x may not respond with the specified bus cycle.
Page 388 INTERFACING WITH EXTERNAL MEMORY Table 15-8. AC Timing Definitions (Continued) Symbol Definition The 87C196CA, 8XC196J x , K x Meets These Specifications (Continued) CLKOUT Low to ALE/ADV# Low (8XC196KS, KT, modes 1 and 2 only) CLLL Time between CLKOUT going low and ALE/ADV# going low. Use to derive other timings. CLKOUT Low to WR# Low CLWL Time between CLKOUT going low and WR# being asserted.
Page 389 8XC196K x , J x , CA USER’S MANUAL Table 15-8. AC Timing Definitions (Continued) Symbol Definition The 87C196CA, 8XC196J x , K x Meets These Specifications (Continued) AD15:8 Hold after WR# High WHAX Minimum time the high byte of the address in 8-bit mode will be valid after WR# inactive. †...
Page 390: Programming The Nonvolatile Memory
Programming the Nonvolatile Memory...
Page 392 CHAPTER 16 PROGRAMMING THE NONVOLATILE MEMORY The 87C196Kx devices contain from 12 Kbytes to 48 Kbytes of one-time-programmable read- only memory (OTPROM). Table 16-1 lists the devices and OTPROM sizes. OTPROM is similar to EPROM, but it comes in an unwindowed package and cannot be erased. You can either pro- gram the OTPROM yourself or have the factory program it as a quick-turn ROM product (this option may not be available for all devices).
Page 393: Programming Methods
PCCBs and unerasable PROM (UPROM) bits. Programming vendors and Intel distributors typically use this mode to program a large number of microcontrollers with a customer’s code and data.
Page 394: Security Features
2013 Lower interrupt vectors 2000 † Intel manufacturing uses this location to determine whether to program the OFD bit. Customers with QROM or MROM codes who desire oscillator failure detection should equate this location to the value 0CDEH. 16.3 SECURITY FEATURES Several security features enable you to control access to both internal and external memory.
Page 395: Controlling Access To Internal Memory
PCCBs. NOTE The developers have made a substantial effort to provide an adequate program protection scheme. However, Intel cannot and does not guarantee that these protection methods will always prevent unauthorized access. 16.3.1.1 Controlling Access to the OTPROM During Normal Operation During normal operation, the lock bits in CCB0 control read and write accesses to the OTPROM.
Page 396: Controlling Access To The Otprom During Programming Modes
PROGRAMMING THE NONVOLATILE MEMORY 16.3.1.2 Controlling Access to the OTPROM During Programming Modes For programming modes, three levels of protection are available: • prohibit all programming • prohibit all programming, but permit authorized ROM dumps • prohibit serial port programming, but permit authorized ROM dumps, auto programming, and slave programming These protection levels are provided by the PCCB0 lock bits, the CCB0 lock bits, and the internal security key (Table 16-4).
Page 397: Controlling Fetches From External Memory
8XC196K x , J x , CA USER’S MANUAL If you want to allow slave and auto programming as well as ROM dumps, leave both PCCB0 lock bits unprogrammed. To protect against unauthorized programming, clear the CCB0 lock bits and program an internal security key.
Page 398 You can verify a UPROM bit to make sure it programmed, but you cannot erase it. For this reason, Intel cannot test the bits before shipment. However, Intel does test the features that the UPROM bits enable, so the only undetectable defects are (unlikely) defects within the UPROM cells them- selves.
Page 399: Enabling The Oscillator Failure Detection Circuitry
† 0778H † Intel manufacturing uses location 2016H to determine whether to program the OFD bit. Customers with QROM or MROM codes who desire the OFD feature should equate location 2016H to the value 0CDEH. 16.4 PROGRAMMING PULSE WIDTH The programming pulse width is controlled in different ways depending on the programming mode.
Page 400 PROGRAMMING THE NONVOLATILE MEMORY The following two examples calculate the PPW_VALUE for a 100-µs pulse width with an 8-MHz and a 16-MHz crystal, respectively. × 8 100 ≈ ------------------ - 1 --------- - 1 PPW_VALUE 4.5552 5 05 H – –...
Page 401: Modified Quick-Pulse Algorithm
A verification error deasserts the PVER signal, but does not stop the programming routine. This process repeats until each OTPROM word has been programmed and verified. Intel guarantees lifetime data retention for a device pro- grammed with the modified quick-pulse algorithm.
Page 402: Programming Mode Pins
PROGRAMMING THE NONVOLATILE MEMORY Auto programming repeats the pulse five times, using the pulse width you specify in the external EPROM. Slave mode repeats the pulse until PROG# is deasserted. In slave programming mode, the PALE# signal controls the pulse width. In all cases, the pulse width must be at least 100 µs for successful programming.
Page 403 8XC196K x , J x , CA USER’S MANUAL Table 16-6. Pin Descriptions (Continued) Special Program- Port Pin Function Type ming Description Signal Mode P2.0 PVER Slave Programming Verification Auto During slave or auto programming, PVER is updated after each programming pulse. A high output signal indicates successful programming of a location, while a low signal indicates a detected error.
Page 404 PROGRAMMING THE NONVOLATILE MEMORY Table 16-6. Pin Descriptions (Continued) Special Program- Port Pin Function Type ming Description Signal Mode P4.7:0, PBUS Slave Address/Command/Data Bus P3.7:0 During slave programming, ports 3 and 4 serve as a bidirectional port with open-drain outputs to pass commands, addresses, and data to or from the device.
Page 405: Entering Programming Modes
8XC196K x , J x , CA USER’S MANUAL 16.7 ENTERING PROGRAMMING MODES To execute programs properly, the device must have these minimum hardware connections: XTAL1 driven, unused input pins strapped, and power and grounds applied. Follow the operating conditions specified in the datasheet. Place the device into programming mode by applying V voltage (+12.5 V) to EA# during the rising edge of RESET#.
Page 406: Power-Up Sequence
PROGRAMMING THE NONVOLATILE MEMORY 16.7.2.1 Power-up Sequence Hold the RESET# pin low while V stabilizes. Allow V and EA# to float during this time. After V and the oscillator stabilize, continue to hold the device in reset and apply V voltage to EA#.
Page 407: Reading The Signature Word And Programming Voltages
8XC196K x , J x , CA USER’S MANUAL 16.8.1 Reading the Signature Word and Programming Voltages The signature word identifies the device; the programming voltages specify the V and V volt- ages required for programming. This information resides in the test ROM at locations 2070H, 2072H, and 2073H;...
Page 408 PROGRAMMING THE NONVOLATILE MEMORY CLOCK XTAL1 RESET# RESET# 0.1 µF kΩ P4.7:0 PBUS P3.7:0 Pullups Required P4.7 - P3.0 P2.6 CPVER P2.4 AINC# P2.2 PROG# P2.1 PALE# P2.0 PVER P0.7/PMODE.3 P0.6/PMODE.2 P0.5/PMODE.1 P0.4/PMODE.0 ANGND 87C196 Device A0256-03 Figure 16-5. Slave Programming Circuit 16-17...
Page 409: Operating Environment
8XC196K x , J x , CA USER’S MANUAL Table 16-9. Slave Programming Mode Memory Map Description Address Comments OTPROM (JV) 2000–DFFFH OTPROM Cells (CA, JT, KT) 2000–9FFFH (KS) 2000–7FFFH (JR, KR) 2000–5FFFH (JQ, KQ) 2000–4FFFH 0778H OTPROM Cell † 0758H UPROM Cell †...
Page 410 PROGRAMMING THE NONVOLATILE MEMORY Address: 201AH, 2018H CCR1, CCR0 Reset State: from CCBs XXH, XXH Reset State: see bit descriptions The chip configuration registers (CCRs) control bus-control signals, bus width, wait states, powerdown mode, and internal memory protection. These registers are loaded from the PCCBs during programming modes and from the CCBs for normal operation.
Page 411: Slave Programming Routines
8XC196K x , J x , CA USER’S MANUAL 16.8.4 Slave Programming Routines The slave programming mode algorithm consists of three routines: the address/command decod- ing routine, the program word routine, and the dump word routine. The address/command decoding routine (Figure 16-7) reads the PBUS and transfers control to the program word or dump word routine based on the value of P3.0.
Page 412 PROGRAMMING THE NONVOLATILE MEMORY Other PMODE = 05H Modes PALE# (P2.1) = 0 Read Data From PBUS PVER Deassert CPVER (P2.0) = 1 Assert PVER PALE# (P2.1)= 0 Check Address Dump Word P3.0 = 1 Routine Program Word Routine A0193-02 Figure 16-7.
Page 413 8XC196K x , J x , CA USER’S MANUAL From Address/ Command Decoder PROG# (P2.2)=0 Lock Bits Verify Read Data Security Key Enabled from PBUS Execute Modified Keys Loop Quick-Pulse Algorithm Match Forever then Return Deassert Programming PVER (P2.0 = 0) Verifies Read Data from PBUS...
Page 414 PROGRAMMING THE NONVOLATILE MEMORY Figure 16-9 shows the timings of the program word command with a repeated programming pulse and auto increment. Asserting PALE# latches the command and address on the PBUS. Asserting PROG# latches the data on the PBUS and starts the programming sequence. The PROG# signal controls the programming pulse width.
Page 415 8XC196K x , J x , CA USER’S MANUAL From Address/ Command Decoder Lock Bits Enabled Get Data from OPTROM PROG# (P2.2) = 0 Write Data to PBUS PROG# (P2.2) = 1 Write 0FFFFH to PBUS PALE# To Address/ (P2.1) = 0 Command Decoder AINC# (P2.4) = 0...
Page 416: Timing Mnemonics
PROGRAMMING THE NONVOLATILE MEMORY Figure 16-11 shows the timings of the dump word command. PROG# governs when the device drives the bus. The timings before the dump word command are the same as those shown in Fig- ure 16-9. In the dump word mode, the AINC# pin can remain active and toggling. The PROG# pin automatically increments the address.
Page 417: Auto Programming Mode
8XC196K x , J x , CA USER’S MANUAL Table 16-10. Timing Mnemonics (Continued) Mnemonic Description PROG# High to Next PROG# Low. PHPL PROG# High to AINC# Low. PHIL AINC# Pulse Width. ILIH PVER Hold After AINC# Low. ILVH AINC# Low to PROG# Low. ILPL PROG# High to PVER Valid.
Page 418 PROGRAMMING THE NONVOLATILE MEMORY 20 pF 20 pF 100 kΩ XTAL1 XTAL2 Reset RESET# +5.0V 1 kΩ 74HC14 1.0µF READY/P5.6 10µF BUSWIDTH/P5.7 +12.50V RD#/P5.3 P0.7/ PMODE.3 P0.6/ P1.2 PMODE.2 P1.1 P0.5/ PMODE.1 AD13:8 A13:8 P0.4/ PMODE.0 ANGND LE OE# 270kΩ ALE/P5.0 27(C)512 P2.7/PACT#...
Page 419: Operating Environment
8XC196K x , J x , CA USER’S MANUAL Table 16-11. Auto Programming Memory Map Address Address Output from Internal Using Circuit 8XC196 OTPROM in Figure Description Device Address 16-12 (A15:0) (P1.2:1, A13:0) 4014H 14H Programming pulse width (PPW) LSB. 4015H 15H Programming pulse width (PPW) MSB.
Page 420 PROGRAMMING THE NONVOLATILE MEMORY Other PMODE = 0CH Modes Lock Bits Enabled Verify Security Key Loop Pass Forever Assert PACT# Load PPW Get External Data Data = 0FFFFH Execute Modified Quick-Pulse Algorithm then Return Error Programming Clear PVER Increment Address Pointer Deassert PACT# Top of Loop Forever...
Page 421: Auto Programming Procedure
8XC196K x , J x , CA USER’S MANUAL If the security key verification is successful, the routine loads the programming pulse width (PPW) value from the external EPROM into the internal PPW register. It then asserts PACT#, in- dicating that programming has begun. (PACT# is also active during reset, although no program- ming is in progress.) PVER is initially asserted and remains asserted unless an error is detected, in which case it is deasserted.
Page 422: Rom-Dump Mode
PROGRAMMING THE NONVOLATILE MEMORY Using another blank EPROM device, follow these steps to program only CCB0. — Place the programming pulse width (PPW) in external locations 14H–15H. — Place the appropriate CCB0 value in external location 4018H. — Place the security key to be verified in external EPROM locations 0020H–002FH. This value must match the security key programmed in step 1.
Page 423: Serial Port Programming Mode
Special software, called IBSP196, simplifies communication between the device and a smart ter- minal. This software is available free of charge through the Intel BBS. (See “Bulletin Board Sys- tem (BBS)” on page 1-9.) NOTE Serial port programming mode has no provision for security-key verification.
Page 424 PROGRAMMING THE NONVOLATILE MEMORY 30 pF 30 pF XTAL1 XTAL2 RESET# 10 µF P0.7/PMODE.3 P0.6/PMODE.2 P0.5/PMODE.1 P0.4/PMODE.0 ANGND READY/P5.6 BUSWIDTH/5.7 P2.1/RXD P2.0/TXD 0.01 µF 87C196 Device 2N2222A 1.8kΩ 1N914 1.8kΩ 2N2907 1.8kΩ 1.8kΩ 1.8kΩ 1N914 10µF A0298-04 Figure 16-14. Serial Port Programming Mode Circuit 16-33...
Page 425: Changing Serial Port Programming Defaults
8XC196K x , J x , CA USER’S MANUAL Because the RISM begins at location 2000H in serial port programming mode, the OTPROM lo- cations are automatically remapped as shown in Table 16-12. For example, to access OTPROM location 2000H in serial port programming mode, you must address it as A000H. Table 16-12.
Page 426: Executing Programs From Internal Ram
PROGRAMMING THE NONVOLATILE MEMORY Table 16-13. Serial Port Programming Default Values and Locations Test ROM Address Test ROM Parameter RISM Default (CA, JQ, JR, Address JT, JV, KQ, KR) (KS, KT) Mode 09H; mode 1, receiver enabled 2213H 2215H SP_CON Baud rate 8067H;...
Page 427: Rism Command Descriptions
8XC196K x , J x , CA USER’S MANUAL Upon entering serial port programming mode, the device enters a waiting loop, called Monitor_Pause, in which it waits for RISM commands to arrive across the serial port. The com- mands are each one byte in length and have values between 00H and 1FH. A value between 00H and 1FH is considered a command unless it follows a data latch enable (SET_DLE_FLAG) com- mand.
Page 428 PROGRAMMING THE NONVOLATILE MEMORY Table 16-15. RISM Command Descriptions (Continued) Value Command Description READ_BYTE Puts the contents of the (byte) memory address pointed to by the ADDR register into the low byte of the DATA register. Memory Addr. ADDR DATA 2215 2214 Before command...
Page 429: Rism Command Examples
8XC196K x , J x , CA USER’S MANUAL Table 16-15. RISM Command Descriptions (Continued) Value Command Description DATA_TO_ADDR Puts the low word of the DATA register into the ADDR register. ADDR DATA Before command After command INDIRECT Puts the word from the memory address pointed to by the ADDR register into the ADDR register.
Page 430: Example 1 - Programming The Ppw
PROGRAMMING THE NONVOLATILE MEMORY 16.10.6.1 Example 1 — Programming the PPW You should specify the programming pulse width before you do any programming or write to any memory locations. This example assumes an 87C196KT device. It loads the SP_PPW register (221CH/221DH) with 8010H, the minimum value for 16-MHz operation.
Page 431: Example 2 - Reading Otprom Contents
8XC196K x , J x , CA USER’S MANUAL 16.10.6.2 Example 2 — Reading OTPROM Contents This example reads the contents of OTPROM address A080H. Because the OTPROM is remapped from 2000H to A000H, the location read is actually 2080H of the program in OTPROM.
Page 432 PROGRAMMING THE NONVOLATILE MEMORY Send Comments (Example 3) DATA ADDR SET_DLE_FLAG. Next data byte is < 1FH. Data. High byte of address 0400H. SET_DLE_FLAG. Next data byte is < 1FH. Data. Low byte of address 0400H. DATA_TO_ADDR. Move address to ADDR. Data.
Page 433: Example 4 - Setting The Pc And Executing The Program
8XC196K x , J x , CA USER’S MANUAL Send Comments (Example 3) DATA ADDR Data. High byte of hex file for location 0405H. Data. Low byte of hex file for location 0404H. WRITE_WORD. Low word of DATA to memory location 0404 (contents of ADDR).
Page 434: Writing To Otprom With Examples 3 And 4
PROGRAMMING THE NONVOLATILE MEMORY Send Comments (Example 4) DATA ADDR WRITE_WORD. Low word of DATA to PC location 005EH (contents of ADDR). Increment ADDR by two. Memory Addresses 005F 005E GO. PUSHes the user PC onto the stack and begins program execution at 0400H. (Had they been changed, GO would also PUSH the PSW and WSR.) You can now interrogate memory locations using RISM commands.
Page 435: Run-Time Programming
8XC196K x , J x , CA USER’S MANUAL 16.11 RUN-TIME PROGRAMMING You can program an OTPROM location during normal code execution. To make the OTPROM array accessible, apply V voltage to EA# while you reset the device. Apply V voltage to the pin during the entire programming process.
Page 436 PROGRAMMING THE NONVOLATILE MEMORY The calling routine must pass two parameters to this routine — the data to be programmed (in DATA_TEMP) and the address (in ADDR_TEMP). PROGRAM: PUSHA ;clear PSW, WSR, INT_MASK, INT_MASK1 WSR,#7BH ;select 32-byte window with EPA0_CON COUNT,#5 ;set up for 5 programming cycles ANDB INT_PEND,#CLEAR_EPA0...
Page 438: Instruction Set Reference
Instruction Set Reference...
Page 440 APPENDIX A INSTRUCTION SET REFERENCE ® This appendix provides reference information for the instruction set of the family of MCS microcontrollers. It defines the processor status word (PSW) flags, describes each instruction, shows the relationships between instructions and processor status word (PSW) flags, and shows hexadecimal opcodes, instruction lengths, and execution times.
Page 441 8XC196K x , J x , CA USER’S MANUAL Table A-1. Opcode Map (Left Half) Opcode SKIP CLRB NOTB NEGB XCHB DECB EXTB INCB SJMP bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 AND 3op ADD 3op ANDB 3op...
Page 442 INSTRUCTION SET REFERENCE Table A-1. Opcode Map (Right Half) Opcode SHRA SHRL SHLL SHRAL NORML SHRB SHLB SHRAB XCHB (Note 1) (Note 1) (Note 1) (Note 1) SCALL bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 SUB 3op...
Page 443 8XC196K x , J x , CA USER’S MANUAL Table A-2. Processor Status Word (PSW) Flags Mnemonic Description The carry flag is set to indicate an arithmetic carry from the MSB of the ALU or the state of the last bit shifted out of an operand. If a subtraction operation generates a borrow, the carry flag is cleared.
Page 444 INSTRUCTION SET REFERENCE Table A-3 shows the effect of the PSW flags or a specified register bit on conditional jump in- structions. Table A-4 defines the symbols used in Table A-6 to show the effect of each instruction on the PSW flags. Table A-3.
Page 445 8XC196K x , J x , CA USER’S MANUAL Table A-5 defines the variables that are used in Table A-6 to represent the instruction operands. Table A-5. Operand Variables Variable Description A 2-bit field within an opcode that selects the basic addressing mode used. This field is present only in those opcodes that allow addressing mode options.
Page 446 INSTRUCTION SET REFERENCE Table A-6. Instruction Set Mnemonic Operation Instruction Format ADD WORDS. Adds the source and DEST, SRC (2 operands) destination word operands and stores the wreg, waop sum into the destination operand. (011001aa) (waop) (wreg) ← (DEST) (DEST) + (SRC) PSW Flag Settings ↑...
Page 447 8XC196K x , J x , CA USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format ADDCB ADD BYTES WITH CARRY. Adds the source DEST, SRC and destination byte operands and the carry ADDCB breg, baop flag (0 or 1) and stores the sum into the (101101aa) (baop) (breg) destination operand.
Page 448 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format ANDB LOGICAL AND BYTES. ANDs the two source DEST, SRC1, SRC2 (3 operands) byte operands and stores the result into the ANDB Dbreg, Sbreg, baop destination operand. The result has ones in (010100aa) (baop) (Sbreg) (Dbreg) only the bit positions in which both operands had a “1”...
Page 449 8XC196K x , J x , CA USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format BMOVI INTERRUPTIBLE BLOCK MOVE. Moves a PTRS, CNTREG block of word data from one location in BMOVI lreg, wreg memory to another. The instruction is (11001101) (wreg) (lreg) identical to BMOV, except that BMOVI is interruptible.
Page 450 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format CLRB CLEAR BYTE. Clears the value of the DEST operand. CLRB breg ← (DEST) (00010001) (breg) PSW Flag Settings — — CLRC CLEAR CARRY FLAG. Clears the carry flag. ←...
Page 451 8XC196K x , J x , CA USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format CMPL COMPARE LONG. Compares the DEST, SRC magnitudes of two double-word (long) CMPL Dlreg, Slreg operands. The operands are specified using (11000101) (Slreg) (Dlreg) the direct addressing mode.
Page 452 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format DIVIDE INTEGERS. Divides the contents of DEST, SRC the destination long-integer operand by the lreg, waop contents of the source integer word operand, (11111110) (100011aa) (waop) (lreg) using signed arithmetic. It stores the quotient into the low-order word of the destination (i.e., the word with the lower address) and the remainder into the high-order word.
Page 453 8XC196K x , J x , CA USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format DIVUB DIVIDE BYTES, UNSIGNED. This instruction DEST, SRC divides the contents of the destination word DIVUB wreg, baop operand by the contents of the source byte (100111aa) (baop) (wreg) operand, using unsigned arithmetic.
Page 454 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format DPTS DISABLE PERIPHERAL TRANSACTION SERVER (PTS). Disables the peripheral DPTS transaction server (PTS). (11101100) ← PTS Disable (PSW.2) PSW Flag Settings — — — — — — ENABLE INTERRUPTS. Enables interrupts following the execution of the next statement.
Page 455 8XC196K x , J x , CA USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format EXTB SIGN-EXTEND SHORT-INTEGER INTO INTEGER. Sign-extends the low-order byte EXTB wreg of the operand throughout the high-order byte (00010110) (wreg) of the operand. if DEST.7 = 1 then ←...
Page 456 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format INCB INCREMENT BYTE. Increments the value of the byte operand by 1. INCB breg ← (DEST) (DEST) + 1 (00010111) (breg) PSW Flag Settings ↑ — JUMP IF BIT IS CLEAR. Tests the specified bit.
Page 457 8XC196K x , J x , CA USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JUMP IF CARRY FLAG IS SET. Tests the carry flag. If the carry flag is clear, control cadd passes to the next sequential instruction. If (11011011) (disp) the carry flag is set, this instruction adds to the program counter the offset between the...
Page 458 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JUMP IF SIGNED GREATER THAN. Tests both the zero flag and the negative flag. If cadd either flag is set, control passes to the next (11010010) (disp) sequential instruction. If both flags are clear, this instruction adds to the program counter NOTE: The displacement (disp) is sign- the offset between the end of this instruction...
Page 459 8XC196K x , J x , CA USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JUMP IF SIGNED LESS THAN. Tests the negative flag. If the flag is clear, control cadd passes to the next sequential instruction. If (11011110) (disp) the negative flag is set, this instruction adds to the program counter the offset between the...
Page 460 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JUMP IF NOT HIGHER (UNSIGNED). Tests both the zero flag and the carry flag. If the cadd carry flag is set and the zero flag is clear, (11010001) (disp) control passes to the next sequential instruction.
Page 461 8XC196K x , J x , CA USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JNVT JUMP IF OVERFLOW-TRAP FLAG IS CLEAR. Tests the overflow-trap flag. If the JNVT cadd flag is set, this instruction clears the flag and (11010100) (disp) passes control to the next sequential instruction.
Page 462 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JUMP IF OVERFLOW-TRAP FLAG IS SET. Tests the overflow-trap flag. If the flag is clear, cadd control passes to the next sequential (11011100) (disp) instruction. If the overflow-trap flag is set, this instruction clears the flag and adds to the NOTE: The displacement (disp) is sign- program counter the offset between the end...
Page 463 8XC196K x , J x , CA USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format LDBSE LOAD BYTE SIGN-EXTENDED. Sign- DEST, SRC extends the value of the source short- LDBSE wreg, baop integer operand and loads it into the (101111aa) (baop) (wreg) destination integer operand.
Page 464 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format MULTIPLY INTEGERS. Multiplies the two DEST, SRC1, SRC2 (3 operands) source integer operands, using signed lreg, wreg, waop arithmetic, and stores the 32-bit result into (11111110) (010011aa) (waop) (wreg) (lreg) the destination long-integer operand.
Page 465 8XC196K x , J x , CA USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format MULU MULTIPLY WORDS, UNSIGNED. Multiplies DEST, SRC1, SRC2 (3 operands) the two source word operands, using MULU lreg, wreg, waop unsigned arithmetic, and stores the 32-bit (010011aa) (waop) (wreg) (lreg) result into the destination double-word operand.
Page 466 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format NEGB NEGATE SHORT-INTEGER. Negates the value of the short-integer operand. NEGB breg ← (DEST) – (DEST) (00010011) (breg) PSW Flag Settings ↑ — NO OPERATION. Does nothing. Control passes to the next sequential instruction.
Page 467 8XC196K x , J x , CA USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format NOTB COMPLEMENT BYTE. Complements the value of the byte operand (replaces each “1” NOTB breg with a “0” and each “0” with a “1”). (00010010) (breg) ←...
Page 468 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format POPA POP ALL. This instruction is used instead of POPF, to support the eight additional POPA interrupts. It pops two words off the stack and (11110101) places the first word into the INT_MASK1/WSR register pair and the second word into the PSW/INT_MASK register-pair.
Page 469 8XC196K x , J x , CA USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format PUSHA PUSH ALL. This instruction is used instead of PUSHF, to support the eight additional PUSHA interrupts. It pushes two words — (11110100) PSW/INT_MASK and INT_MASK1/WSR —...
Page 470 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format RESET SYSTEM. Initializes the PSW to zero, the PC to 2080H, and the pins and SFRs to their reset values. Executing this instruction (11111111) causes the RESET# pin to be pulled low for 16 state times.
Page 471 8XC196K x , J x , CA USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SHIFT WORD LEFT. Shifts the destination word operand to the left as many times as wreg,#count specified by the count operand. The count (00001001) (count) (wreg) may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive,...
Page 472 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SHLL SHIFT DOUBLE-WORD LEFT. Shifts the destination double-word operand to the left SHLL lreg,#count as many times as specified by the count (00001101) (count) (breg) operand. The count may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive, or as the content of any SHLL...
Page 473 8XC196K x , J x , CA USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SHRA ARITHMETIC RIGHT SHIFT WORD. Shifts the destination word operand to the right as SHRA wreg,#count many times as specified by the count (00001010) (count) (wreg) operand.
Page 474 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SHRAL ARITHMETIC RIGHT SHIFT DOUBLE- WORD. Shifts the destination double-word SHRAL lreg,#count operand to the right as many times as (00001110) (count) (lreg) specified by the count operand. The count may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive, SHRAL...
Page 475 8XC196K x , J x , CA USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SHRL LOGICAL RIGHT SHIFT DOUBLE-WORD. Shifts the destination double-word operand to SHRL lreg,#count the right as many times as specified by the (00001100) (count) (lreg) count operand.
Page 476 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format STORE WORD. Stores the value of the SRC, DEST source (leftmost) word operand into the wreg, waop destination (rightmost) operand. (110000aa) (waop) (wreg) ← (DEST) (SRC) PSW Flag Settings —...
Page 477 8XC196K x , J x , CA USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SUBB SUBTRACT BYTES. Subtracts the source DEST, SRC (2 operands) byte operand from the destination byte SUBB breg, baop operand, stores the result in the destination (011110aa) (baop) (breg) operand, and sets the carry flag as the complement of borrow.
Page 478 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format TIJMP TABLE INDIRECT JUMP. Causes execution to continue at an address selected from a TIJMP TBASE, [INDEX], #MASK table of addresses. (11100010) [INDEX] (#MASK) (TBASE) The TIJMP instruction reduces the interrupt response time associated with servicing multiple interrupt sources that are multiplexed NOTE: TIJMP multiplies OFFSET by two...
Page 479 8XC196K x , J x , CA USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format TRAP SOFTWARE TRAP. This instruction causes an interrupt-call that is vectored through TRAP location 2010H. The operation of this (11110111) instruction is not affected by the state of the interrupt enable flag (I) in the PSW.
Page 480 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format XORB LOGICAL EXCLUSIVE-OR BYTES. XORs DEST, SRC the source byte operand with the destination XORB breg, baop byte operand and stores the result in the (100101aa) (baop) (breg) destination operand.
Page 481 8XC196K x , J x , CA USER’S MANUAL Table A-7. Instruction Opcodes Hex Code Instruction Mnemonic SKIP XCH Direct SHRA XCH Indexed SHRL SHLL SHRAL NORML Reserved CLRB NOTB NEGB XCHB Direct DECB EXTB INCB SHRB SHLB SHRAB XCHB Indexed 1C–1F Reserved (Note 1) 20–27...
Page 482 INSTRUCTION SET REFERENCE Table A-7. Instruction Opcodes (Continued) Hex Code Instruction Mnemonic ADD Indexed (3 ops) SUB Direct (3 ops) SUB Immediate (3 ops) SUB Indirect (3 ops) SUB Indexed (3 ops) MULU Direct (3 ops) MULU Immediate (3 ops) MULU Indirect (3 ops) MULU Indexed (3 ops) ANDB Direct (3 ops)
Page 483 8XC196K x , J x , CA USER’S MANUAL Table A-7. Instruction Opcodes (Continued) Hex Code Instruction Mnemonic ANDB Direct (2 ops) ANDB Immediate (2 ops) ANDB Indirect (2 ops) ANDB Indexed (2 ops) ADDB Direct (2 ops) ADDB Immediate (2 ops) ADDB Indirect (2 ops) ADDB Indexed (2 ops) SUBB Direct (2 ops)
Page 484 INSTRUCTION SET REFERENCE Table A-7. Instruction Opcodes (Continued) Hex Code Instruction Mnemonic CMPB Indirect CMPB Indexed DIVUB Direct DIVUB Immediate DIVUB Indirect DIVUB Indexed LD Direct LD Immediate LD Indirect LD Indexed ADDC Direct ADDC Immediate ADDC Indirect ADDC Indexed SUBC Direct SUBC Immediate SUBC Indirect...
Page 485 8XC196K x , J x , CA USER’S MANUAL Table A-7. Instruction Opcodes (Continued) Hex Code Instruction Mnemonic ST Indexed STB Direct CMPL STB Indirect STB Indexed PUSH Direct PUSH Immediate PUSH Indirect PUSH Indexed POP Direct BMOVI POP Indirect POP Indexed JNST JNVT...
Page 486 INSTRUCTION SET REFERENCE Table A-7. Instruction Opcodes (Continued) Hex Code Instruction Mnemonic PUSHF POPF PUSHA POPA IDLPD TRAP CLRC SETC CLRVT DIV/DIVB/MUL/MULB (Note 2) NOTES: For the 8XC196KS and KT only, this opcode is reserved, but it does not generate an unimple- mented opcode interrupt.
Page 487 8XC196K x , J x , CA USER’S MANUAL Table A-8. Instruction Lengths and Hexadecimal Opcodes Arithmetic (Group I) Indirect Indexed Direct Immediate (Note 1) (Notes 1, 2) Mnemonic Length Length Opcode Length Opcode Length Opcode Opcode ADD (2 ops) ADD (3 ops) ADDB (2 ops) ADDB (3 ops)
Page 488 INSTRUCTION SET REFERENCE Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued) Arithmetic (Group II) Indirect Indexed Direct Immediate (Note 1) (Notes 1, 2) Mnemonic Length Length Opcode Length Opcode Length Opcode Opcode FE 8C FE 8D FE 8E FE 8F DIVB FE 9C FE 9D...
Page 489 8XC196K x , J x , CA USER’S MANUAL Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued) Stack Indirect Indexed Direct Immediate (Note 1) (Notes 1, 2) Mnemonic Length Length Opcode Length Opcode Length Opcode Opcode — — POPA — —...
Page 490 INSTRUCTION SET REFERENCE Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued) Jump Length Opcode Length Opcode Length Opcode Length Opcode Indirect Indexed Direct Immediate (Note 1) (Notes 1, 2) Mnemonic Length Length Opcode Length Opcode Length Opcode Opcode — — —...
Page 491 8XC196K x , J x , CA USER’S MANUAL Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued) Conditional Jump Indexed Direct Immediate Indirect (Notes 1, 2) Mnemonic Length Length Opcode Length Opcode Length Opcode Opcode DJNZ — — — — —...
Page 492 INSTRUCTION SET REFERENCE Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued) Shift Direct Immediate Indirect Indexed Mnemonic Length Opcode Length Opcode Length Opcode Length Opcode NORML — — — — — — — — — — — — SHLB — —...
Page 493 8XC196K x , J x , CA USER’S MANUAL Table A-9 lists instructions alphabetically within groups, along with their execution times, ex- pressed in state times. Table A-9. Instruction Execution Times (in State Times) Arithmetic (Group I) Indirect Indexed Mnemonic Direct Immed.
Page 494 INSTRUCTION SET REFERENCE Table A-9. Instruction Execution Times (in State Times) (Continued) Arithmetic (Group II) Indirect Indexed Mnemonic Direct Immed. Normal Autoinc. Short Long Reg. Mem. Reg. Mem. Reg. Mem. Reg. Mem. DIVB DIVU DIVUB MUL (2 ops) MUL (3 ops) MULB (2 ops) MULB (3 ops) MULU (2 ops)
Page 495 8XC196K x , J x , CA USER’S MANUAL Table A-9. Instruction Execution Times (in State Times) (Continued) Stack (Register) Indirect Indexed Mnemonic Direct Immed. Normal Autoinc. Short Long Reg. Mem. Reg. Mem. Reg. Mem. Reg. Mem. — POPA — —...
Page 496 INSTRUCTION SET REFERENCE Table A-9. Instruction Execution Times (in State Times) (Continued) Data Mnemonic Indirect BMOV register/register 6 + 8 per word memory/register 6 + 11 per word memory/memory 6 + 14 per word BMOVI register/register 7 + 8 per word + 14 per interrupt memory/register 7 + 11 per word + 14 per interrupt memory/memory...
Page 497 8XC196K x , J x , CA USER’S MANUAL Table A-9. Instruction Execution Times (in State Times) (Continued) Call (Memory) Indirect Indexed Mnemonic Direct Immed. Normal Autoinc. Short Long LCALL — — — — — — — — — — SCALL —...
Page 498 INSTRUCTION SET REFERENCE Table A-9. Instruction Execution Times (in State Times) (Continued) Shift Mnemonic Direct NORML 8 + 1 per shift (9 for 0 shift) 6 + 1 per shift (7 for 0 shift) SHLB 6 + 1 per shift (7 for 0 shift) SHLL 7 + 1 per shift (8 for 0 shift) 6 + 1 per shift (7 for 0 shift)
Page 500 Signal Descriptions...
Page 502 APPENDIX B SIGNAL DESCRIPTIONS This appendix provides reference information for the pin functions of the 8XC196Kx, 8XC196Jx, and 87C196CA. SIGNAL NAME CHANGES The names of some 8XC196Kx and 8XC196Jx signals have been changed for consistency with ® other MCS 96 microcontrollers. Table B-1 lists the old and new names. Table B-1.
Page 503 8XC196K x , J x , CA USER’S MANUAL Table B-2. 8XC196K x Signals Arranged by Functional Categories Programming Input/Output Input/Output (Cont’d) Bus Control & Status Control P0.7:0/ACH7:0 P6.5/SD0 AINC# ALE/ADV# P1.0/EPA0/T2CLK P6.6/SC1 CPVER BHE#/WRH# P1.1/EPA1 P6.7/SD1 PACT# BREQ# P1.2/EPA2/T2DIR PALE# BUSWIDTH P1.7:3/EPA7:3...
Page 504 SIGNAL DESCRIPTIONS P5.7 / BUSWIDTH P6.2 / T1CLK AD15 / P4.7 / PBUS.15 P6.1 / EPA9 / COMP1 AD14 / P4.6 / PBUS.14 P6.0 / EPA8 / COMP0 AD13 / P4.5 / PBUS.13 P1.0 / EPA0 / T2CLK AD12 / P4.4 / PBUS.12 P1.1 / EPA1 AD11 / P4.3 / PBUS.11 P1.2 / EPA2 / T2DIR...
Page 505 8XC196K x , J x , CA USER’S MANUAL Table B-3. 8XC196J x Signals Arranged by Functional Categories Programming Input/Output Input/Output (Cont’d) Bus Control & Status Control P0.7:2/ACH7:2 P6.1/EPA9/COMP1 AINC# ALE/ADV# P1.0/EPA0/T2CLK P6.4/SC0 CPVER CLKOUT P1.1/EPA1 P6.5/SD0 PACT# P1.2/EPA2/T2DIR P6.6/SC1 PALE# WR#/WRL# P1.3/EPA3...
Page 506 SIGNAL DESCRIPTIONS AD14 / P4.6 / PBUS.14 P6.1 / EPA9 / COMP1 AD13 / P4.5 / PBUS.13 P6.0 / EPA8 / COMP0 AD12 / P4.4 / PBUS.12 P1.0 / EPA0 / T2CLK AD11 / P4.3 / PBUS.11 P1.1 / EPA1 8XC196J x AD10 / P4.2 / PBUS.10 P1.2 / EPA2 / T2DIR...
Page 507 8XC196K x , J x , CA USER’S MANUAL Table B-4. 87C196CA Signals Arranged by Functional Categories Programming Input/Output Input/Output (Cont’d) Bus Control & Status Control P0.7:2/ACH7:2 P6.4/SC0 AINC# ALE/ADV# P1.0/EPA0/T2CLK P6.5/SD0 CPVER WRH# P1.1/EPA1 P6.6/SC1 PACT# CLKOUT P1.2/EPA2/T2DIR P6.7/SD1 PALE# READY P1.3/EPA3...
Page 508 SIGNAL DESCRIPTIONS AD15 / P4.7 / PBUS.15 AD14 / P4.6 / PBUS.14 AD13 / P4.5 / PBUS.13 P6.1 / EPA9 / COMP1 AD12 / P4.4 / PBUS.12 P6.0 / EPA8 / COMP0 AD11 / P4.3 / PBUS.11 P1.0 / EPA0 / T2CLK 87C196CA AD10 / P4.2 / PBUS.10 P1.1 / EPA1...
Page 509 8XC196K x , J x , CA USER’S MANUAL SIGNAL DESCRIPTIONS Table B-5 defines the columns used in Table B-6, which describes the signals. Table B-5. Description of Columns of Table B-6 Column Heading Description Name Lists the signals, arranged alphabetically. Many pins have two functions, so there are more entries in this column than there are pins.
Page 510 SIGNAL DESCRIPTIONS Table B-6. Signal Descriptions (Continued) Name Type Description AD15:0 Address/Data Lines These pins provide a multiplexed address and data bus. During the address phase of the bus cycle, address bits 0–15 are presented on the bus and can be latched using ALE or ADV#.
Page 511 8XC196K x , J x , CA USER’S MANUAL Table B-6. Signal Descriptions (Continued) Name Type Description †† BHE# Byte High Enable The chip configuration register 0 (CCR0) determines whether this pin functions as BHE# or WRH#. CCR0.2=1 selects BHE#; CCR0.2=0 selects WRH#. During 16-bit bus cycles, this active-low output signal is asserted for word reads and writes and high-byte reads and writes to external memory.
Page 512 SIGNAL DESCRIPTIONS Table B-6. Signal Descriptions (Continued) Name Type Description CPVER Cumulative Program Verification During slave programming, a high signal indicates that all locations programmed correctly, while a low signal indicates that an error occurred during one of the programming operations. On the 8XC196K x , CPVER is multiplexed with P2.6 and HLDA#.
Page 513 8XC196K x , J x , CA USER’S MANUAL Table B-6. Signal Descriptions (Continued) Name Type Description EXTINT External Interrupt In normal operating mode, a rising edge on EXTINT sets the EXTINT interrupt pending flag. EXTINT is sampled during phase 2 (CLKOUT high). The minimum high time is one state time.
Page 514 SIGNAL DESCRIPTIONS Table B-6. Signal Descriptions (Continued) Name Type Description †† Nonmaskable Interrupt In normal operating mode, a rising edge on NMI causes a vector through the NMI interrupt at location 203EH. NMI must be asserted for greater than one state time to guarantee that it is recognized.
Page 515 8XC196K x , J x , CA USER’S MANUAL Table B-6. Signal Descriptions (Continued) Name Type Description P2.7:0 (K x ) Port 2 P2.7:6, P2.4, This is a standard bidirectional port that is multiplexed with individually P2.2:0 (J x , CA) selectable special-function signals.
Page 516 SIGNAL DESCRIPTIONS Table B-6. Signal Descriptions (Continued) Name Type Description P6.7:0 Port 6 This is a standard 8-bit bidirectional port. Port 6 is multiplexed as follows: P6.0/EPA8/COMP0, P6.1/EPA9/COMP1, P6.2/T1CLK, P6.3/T1DIR, P6.4/SC0, P6.5/SD0, P6.6/SC1, and P6.7/SD1. P6.2 and P6.3 are not implemented on the 8XC196J x and 87C196CA. PACT# Programming Active During auto programming or ROM-dump, a low signal indicates that...
Page 517 8XC196K x , J x , CA USER’S MANUAL Table B-6. Signal Descriptions (Continued) Name Type Description Program Verification PVER During slave or auto programming, PVER is updated after each programming pulse. A high output signal indicates successful programming of a location, while a low signal indicates a detected error.
Page 518 SIGNAL DESCRIPTIONS Table B-6. Signal Descriptions (Continued) Name Type Description † SLP7:0 Slave Port Address/Data bus Slave port address/data bus in multiplexed mode and slave port data bus in demultiplexed mode. In multiplexed mode, SLP1 is the source of the internal control signal, SLP_ADDR.
Page 519 8XC196K x , J x , CA USER’S MANUAL Table B-6. Signal Descriptions (Continued) Name Type Description † T1DIR Timer 1 External Direction External direction (up/down) for timer 1. Timer 1 increments when T1DIR is high and decrements when it is low. Also used in conjunction with T1CLK for quadrature counting mode.
Page 520 SIGNAL DESCRIPTIONS Table B-6. Signal Descriptions (Continued) Name Type Description † WRH# Write High The chip configuration register 0 (CCR0) determines whether this pin functions as BHE# or WRH#. CCR0.2=1 selects BHE#; CCR0.2=0 selects WRH#. During 16-bit bus cycles, this active-low output signal is asserted for high-byte writes and word writes to external memory.
Page 521 8XC196K x , J x , CA USER’S MANUAL Table B-8. 8XC196K x Pin Status Upon RESET# Multiplexed During RESET# Power- Pins Inactive Idle With Active down (Note 9) P0.7:0 ACH7:0 P1.0 EPA0/T2CLK (Note 3) (Note 3) P1.1 EPA1 (Note 3) (Note 3) P1.2 EPA2/T2DIR...
Page 522 SIGNAL DESCRIPTIONS Table B-8. 8XC196K x Pin Status (Continued) Upon RESET# Multiplexed During RESET# Power- Pins Inactive Idle With Active down (Note 9) XTAL1 — Osc input, Osc input, Osc input, HiZ Osc input, HiZ XTAL2 — Osc output, Osc output, Osc output, (Note 5) LoZ0/1...
Page 523 8XC196K x , J x , CA USER’S MANUAL Table B-9. 8XC196J x Pin Status (Continued) Upon RESET# Multiplexed During RESET# Pins Inactive Idle Power-down With Active (Note 8) P6.4 (Note 3) (Note 3) P6.5 (Note 3) (Note 3) P6.6 (Note 3) (Note 3) P6.7...
Page 524 SIGNAL DESCRIPTIONS Table B-10. 87C196CA Pin Status (Continued) Multiplexed During RESET# Upon RESET# Pins Idle Power-down With Active Inactive (Note 9) P4.7:0 AD15:8 (Note 6) (Note 6) P5.0 ALE/ADV# (Note 1) (Note 1) P5.2 WR#/WRL# (Note 3) (Note 3) P5.3 (Note 3) (Note 3) P5.4...
Page 526 Registers...
Page 528 APPENDIX C REGISTERS This appendix provides reference information about the device registers. Table C-1 lists the mod- ules and major components of the device with their related configuration and status registers. Ta- ble C-2 lists the registers, arranged alphabetically by mnemonic, along with their names, addresses, and reset values.
Page 529 8XC196K x, J x , CA USER’S MANUAL Table C-1. Modules and Related Registers (Continued) Slave Port Synch. Serial Port Timers Serial Port (8XC196K x ) ( x = 0–1) ( x = 1–2) TIMER x SBUF_RX SLP_CMD SSIO_BAUD SBUF_TX SLP_CON SSIO x _BUF T x CONTROL...
Page 530 REGISTERS Table C-2. Register Name, Address, and Reset Status (Continued) Binary Reset Value Register Register Name Mnemonic Address High † †† CAN_MSG x ID1 (CA) CAN Message Object Ident 1 1E y 3H Unchanged † †† CAN_MSG x ID2 (CA) CAN Message Object Ident 2 1E y 4H Unchanged...
Page 531 8XC196K x, J x , CA USER’S MANUAL Table C-2. Register Name, Address, and Reset Status (Continued) Binary Reset Value Register Register Name Mnemonic Address High EPA7_CON (K x ) EPA Capture/Comp 7 Control 1F7CH 0000 0000 EPA7_TIME (K x ) EPA Capture/Comp 7 Time 1F7EH XXXX...
Page 532 REGISTERS Table C-2. Register Name, Address, and Reset Status (Continued) Binary Reset Value Register Register Name Mnemonic Address High P6_PIN Port 6 Pin Input 1FD7H XXXX XXXX P6_REG Port 6 Data Output 1FD5H 1111 1111 PPW (or SP_PPW) Programming Pulse Width Program Status Word PTSSEL PTS Select...
Page 533 8XC196K x, J x , CA USER’S MANUAL AD_COMMAND Address: 1FACH AD_COMMAND Reset State: The A/D command (AD_COMMAND) register selects the A/D channel number to be converted, controls whether the A/D converter starts immediately or with an EPA command, and selects the conversion mode.
Page 534 REGISTERS AD_RESULT (Read) Address: 1FAAH AD_RESULT (Read) Reset State: 7F80H The A/D result (AD_RESULT) register consists of two bytes. The high byte contains the eight most- significant bits from the A/D converter. The low byte contains the two least-significant bits from a ten- bit A/D conversion, indicates the A/D channel number that was used for the conversion, and indicates whether a conversion is currently in progress.
Page 535 8XC196K x, J x , CA USER’S MANUAL AD_RESULT (Write) Address: 1FAAH AD_RESULT (Write) Reset State: 7F80H The high byte of the A/D result (AD_RESULT) register can be written to set the reference voltage for the A/D threshold-detection modes. REFV7 REFV6 REFV5 REFV4...
Page 536 REGISTERS AD_TEST Address: 1FAEH AD_TEST Reset State: The A/D test (AD_TEST) register enables conversions on ANGND and V and specifies adjustments for DC offset errors. Its functions allow you to perform two conversions, one on ANGND and one on V .
Page 537 8XC196K x, J x , CA USER’S MANUAL AD_TIME Address: 1FAFH AD_TIME Reset State: The A/D time (AD_TIME) register programs the sample window time and the conversion time for each bit. SAM2 SAM1 SAM0 CONV4 CONV3 CONV2 CONV1 CONV0 Function Number Mnemonic SAM2:0...
Page 538 REGISTERS CAN_BTIME0 Address: 1E3FH CAN_BTIME0 Reset State: Unchanged (87C196CA) Program the CAN bit timing 0 (CAN_BTIME0) register to define the length of one time quantum and the maximum number of time quanta by which a bit time can be modified for resynchronization. 87C196CA SJW1 SJW0...
Page 539 8XC196K x, J x , CA USER’S MANUAL CAN_BTIME1 Address: 1E4FH CAN_BTIME1 Reset State: Unchanged (87C196CA) Program the CAN bit timing 1 (CAN_BTIME1) register to define the sample time and the sample mode. The CAN controller samples the bus during the last one (in single-sample mode) or three (in three-sample mode) time quanta of t , and initiates a transmission at the end of t TSEG...
Page 540 REGISTERS CAN_CON Address: 1E00H CAN_CON Reset State: (87C196CA) Program the CAN control (CAN_CON) register to control write access to the bit timing registers, to enable and disable CAN interrupts, and to control access to the CAN bus. 87C196CA — — —...
Page 541 8XC196K x, J x , CA USER’S MANUAL CAN_CON Address: 1E00H CAN_CON (Continued) Reset State: (87C196CA) Program the CAN control (CAN_CON) register to control write access to the bit timing registers, to enable and disable CAN interrupts, and to control access to the CAN bus. 87C196CA —...
Page 542 REGISTERS CAN_EGMSK Address: Table C-3 CAN_EGMSK Reset State: (87C196CA) Program the CAN extended global mask (CAN_EGMSK) register to mask (“don’t care”) specific message identifier bits for extended message objects. 87C196CA MSK4 MSK3 MSK2 MSK1 MSK0 — — — MSK12 MSK11 MSK10 MSK9 MSK8...
Page 543 8XC196K x, J x , CA USER’S MANUAL CAN_INT Address: 1E5FH CAN_INT Reset State: read-only (87C196CA) The CAN interrupt pending (CAN_INT) register indicates the source of the highest priority pending interrupt. If a status change generated the interrupt request, software can read the status register (CAN_STAT) to determine whether the interrupt request was caused by an abnormal error rate, a successful reception, a successful transmission, or a new error.
Page 544 REGISTERS CAN_MSGxCFG Address: Table C-4 CAN_MSG x CFG Reset State: x = 1–15 (87C196CA) Program the CAN message object x configuration (CAN_MSG x CFG) register to specify a message object’s data length, transfer direction, and identifier type. 87C196CA DLC3 DLC2 DLC1 DLC0 —...
Page 545 8XC196K x, J x , CA USER’S MANUAL CAN_MSGxCON0 Address: Table C-5 CAN_MSG x CON0 Reset State: x = 1–15 (87C196CA) Program the CAN message object x control 0 (CAN_MSG x CON0) register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt.
Page 546 REGISTERS CAN_MSGxCON0 Address: Table C-5 CAN_MSG x CON0 (Continued) Reset State: x = 1–15 (87C196CA) Program the CAN message object x control 0 (CAN_MSG x CON0) register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt.
Page 547 8XC196K x, J x , CA USER’S MANUAL CAN_MSGxCON1 Address: Table C-6 CAN_MSG x CON1 Reset State: x = 1–15 (87C196CA) The CAN message object x control 1 (CAN_MSG x CON1) register indicates whether a message object has been updated, whether a message has been overwritten, whether the CPU is updating the message, and whether a transmission or reception is pending.
Page 548 REGISTERS CAN_MSGxCON1 Address: Table C-6 CAN_MSG x CON1 (Continued) Reset State: x = 1–15 (87C196CA) The CAN message object x control 1 (CAN_MSG x CON1) register indicates whether a message object has been updated, whether a message has been overwritten, whether the CPU is updating the message, and whether a transmission or reception is pending.
Page 549 8XC196K x, J x , CA USER’S MANUAL CAN_MSGxDATA0–7 Address: Table C-7 CAN_MSG x DATA0–7 Reset State: x = 1–15 (87C196CA) The CAN message object data (CAN_MSG x DATA0–7) registers contain data to be transmitted or data received. Any unused data bytes have random values that change during operation. 87C196CA CAN_MSG x DATA7 Data 7...
Page 550 REGISTERS CAN_MSGxDATA0–7 Table C-7. CAN_MSG x DATA0–7 Addresses Register Address Register Address Register Address CAN_MSG1DATA0 1E17H CAN_MSG6DATA0 1E67H CAN_MSG11DATA0 1EB7H CAN_MSG1DATA1 1E18H CAN_MSG6DATA1 1E68H CAN_MSG11DATA1 1EB8H CAN_MSG1DATA2 1E19H CAN_MSG6DATA2 1E69H CAN_MSG11DATA2 1EB9H CAN_MSG1DATA3 1E1AH CAN_MSG6DATA3 1E6AH CAN_MSG11DATA3 1EBAH CAN_MSG1DATA4 1E1BH CAN_MSG6DATA4 1E6BH CAN_MSG11DATA4...
Page 551 8XC196K x, J x , CA USER’S MANUAL CAN_MSGxID0–3 Address: Table C-8 CAN_MSG x ID0–3 Reset State: x = 1–15 (87C196CA) Write the message object’s identifier to the CAN message object x identifier (CAN_MSG x ID0–3) register. Software can change the identifier during normal operation. Clear the MSGVAL bit in the corresponding CAN_MSG x CON0 register to prevent the CPU from accessing the message object, change the identifier in CAN_MSG x ID0–3, then set the MSGVAL bit to allow access.
Page 552 REGISTERS CAN_MSGxID0–3 Table C-8. CAN_MSG x ID0–3 Addresses Register Address Register Address Register Address CAN_MSG1ID0 1E12H CAN_MSG6ID0 1E62H CAN_MSG11ID0 1EB2H CAN_MSG1ID1 1E13H CAN_MSG6ID1 1E63H CAN_MSG11ID1 1EB3H CAN_MSG1ID2 1E14H CAN_MSG6ID2 1E64H CAN_MSG11ID2 1EB4H CAN_MSG1ID3 1E15H CAN_MSG6ID3 1E65H CAN_MSG11ID3 1EB5H CAN_MSG2ID0 1E22H CAN_MSG7ID0 1E72H CAN_MSG12ID0...
Page 553 8XC196K x, J x , CA USER’S MANUAL CAN_MSK15 CAN_MSK15 Address: Table C-9 (87C196CA) Reset State: Program the CAN message 15 mask (CAN_MSK15) register to mask (“don’t care”) specific message identifier bits for message 15 in addition to those bits masked by a global mask (CAN_EGMSK or CAN_SGMSK).
Page 554 REGISTERS CAN_SGMSK Address: 1E07H, 1E06H CAN_SGMSK Reset State: Unchanged (87C196CA) Program the CAN standard global mask (CAN_SGMSK) register to mask (“don’t care”) specific message identifier bits for standard message objects. 87C196CA MSK20 MSK19 MSK18 — — — — — MSK28 MSK27 MSK26 MSK25...
Page 555 8XC196K x, J x , CA USER’S MANUAL CAN_STAT Address: 1E01H CAN_STAT Reset State: (87C196CA) The CAN status (CAN_STAT) register reflects the current status of the CAN peripheral. 87C196CA BUSOFF WARN — RXOK TXOK LEC2 LEC1 LEC0 Function Number Mnemonic BUSOFF Bus-off Status The CAN peripheral sets this read-only bit to indicate that it has isolated...
Page 556 REGISTERS CCR0 Address: 2018H CCR0 Reset State: The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus width. LOC1 LOC0 IRC1 IRC0...
Page 557 8XC196K x, J x , CA USER’S MANUAL CCR0 Address: 2018H CCR0 (Continued) Reset State: The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus width.
Page 558 REGISTERS CCR1 Address: 201AH CCR1 Reset State: The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width. CA, J x , KQ, KR IRC2 KS, KT...
Page 559 8XC196K x, J x , CA USER’S MANUAL CCR1 Address: 201AH CCR1 (Continued) Reset State: The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width. CA, J x , KQ, KR IRC2 KS, KT...
Page 560 REGISTERS COMPx_CON Address: Table C-10 COMP x _CON Reset State: x = 0–1 The EPA compare control (COMP x _CON) registers determine the function of the EPA compare channels. Function Number Mnemonic Time Base Select Specifies the reference timer. 1 = timer 2 is the reference timer and timer 1 is the opposite timer 0 = timer 1 is the reference timer and timer 2 is the opposite timer A compare event (start of an A/D conversion;...
Page 561 8XC196K x, J x , CA USER’S MANUAL COMPx_CON Address: Table C-10 COMP x _CON Reset State: (Continued) The EPA compare control (COMP x _CON) registers determine the function of the EPA compare channels. Function Number Mnemonic Reset Opposite Timer and Reset Timer These bits control whether an EPA compare event resets the reference timer or the opposite timer.
Page 562 REGISTERS COMPx_TIME Address: Table C-11 COMP x _TIME Reset State: x = 0–1 The EPA compare x time (COMP x _TIME) registers are the event-time registers for the EPA compare channels; they are functionally identically to the EPA x _TIME registers. The EPA triggers a compare event when the reference timer matches the value in COMP x _TIME.
Page 563 8XC196K x, J x , CA USER’S MANUAL EPA_MASK Address: 1FA0H EPA_MASK Reset State: 0000H The EPA interrupt mask (EPA_MASK) register enables or disables (masks) interrupts associated with the multiplexed EPA x interrupt. CA, Jx — — — — EPA8 EPA9 OVR0 OVR1...
Page 564 REGISTERS EPA_MASK1 Address: 1FA4H EPA_MASK1 Reset State: The EPA interrupt mask 1 (EPA_MASK1) register enables or disables (masks) interrupts associated with the EPA x interrupt. — — — — COMP0 COMP1 OVRTM1 OVRTM2 Function Number Reserved; for compatibility with future devices, write zeros to these bits. Setting a bit enables the corresponding interrupt as a multiplexed EPA x interrupt source.
Page 565 8XC196K x, J x , CA USER’S MANUAL EPA_PEND Address: 1FA2H EPA_PEND Reset State: 0000H When hardware detects a pending EPA x interrupt, it sets the corresponding bit in EPA interrupt pending (EPA_PEND or EPA_PEND1) registers. The EPAIPV register contains a number that identifies the highest priority, active, multiplexed interrupt source.
Page 566 REGISTERS EPA_PEND1 Address: 1FA6H EPA_PEND1 Reset State: When hardware detects a pending EPA x interrupt, it sets the corresponding bit in EPA interrupt pending (EPA_PEND or EPA_PEND1) registers. The EPAIPV register contains a number that identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA interrupt pending bit associated with the EPAIPV priority value is cleared.
Page 567 8XC196K x, J x , CA USER’S MANUAL EPAx_CON Address: Table C-12 EPA x _CON Reset State: x = 0–9 (8XC196K x ) x = 0–3, 8, 9 (8XC196CA, J x ) The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels.
Page 568 REGISTERS EPAx_CON Address: Table C-12 EPA x _CON (Continued) Reset State: x = 0–9 (8XC196K x ) x = 0–3, 8, 9 (8XC196CA, J x ) The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels.
Page 569 8XC196K x, J x , CA USER’S MANUAL EPAx_CON Address: Table C-12 EPA x _CON (Continued) Reset State: x = 0–9 (8XC196K x ) x = 0–3, 8, 9 (8XC196CA, J x ) The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels.
Page 570 REGISTERS EPAx_CON Table C-12. EPA x _CON Addresses and Reset Values Register Address Reset Value Register Address Reset Value † EPA0_CON 1F60H EPA5_CON 1F74H † EPA1_CON 1F64H F700H EPA6_CON 1F78H EPA2_CON 1F68H EPA7_CON 1F7CH EPA3_CON 1F6CH F700H EPA8_CON 1F80H † EPA4_CON 1F70H EPA9_CON...
Page 571 8XC196K x, J x , CA USER’S MANUAL EPAx_TIME Address: Table C-13 EPA x _TIME Reset State: x = 0–9 (8XC196K x ) x = 0–3, 8, 9 (87C196CA, 8XC196J x ) The EPA time (EPA x _TIME) registers are the event-time registers for the EPA channels. In capture mode, the value of the reference timer is captured in EPA x _TIME when an input transition occurs.
Page 572 REGISTERS EPAIPV Address: 1FA8H EPAIPV Reset State: When an EPA x interrupt occurs, the EPA interrupt priority vector register (EPAIPV) contains a number that identifies the highest priority, active, multiplexed interrupt source (see Table C-14). EPAIPV allows software to branch via the TIJMP instruction to the correct interrupt service routine when EPA x is activated.
Page 573 8XC196K x, J x , CA USER’S MANUAL INT_MASK Address: INT_MASK Reset State: The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupts. (The EI and DI instructions enable and disable servicing of all maskable interrupts.). INT_MASK is the low byte of the program status word (PSW).
Page 574 REGISTERS INT_MASK1 Address: INT_MASK1 Reset State: The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupts. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can be read from or written to as a byte register. PUSHA saves this register on the stack and POPA restores it. 87C196CA EXTINT SSIO1...
Page 575 8XC196K x, J x , CA USER’S MANUAL INT_PEND Address: INT_PEND Reset State: When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit.
Page 576 REGISTERS INT_PEND1 Address: INT_PEND1 Reset State: When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit. 87C196CA EXTINT SSIO1...
Page 577 8XC196K x, J x , CA USER’S MANUAL ONES_REG Address: ONES_REG Reset State: FFFFH The two-byte ones register (ONES_REG) is always equal to FFFFH. It is useful as a fixed source of all ones for comparison operations. One (high byte) One (low byte) Function Number...
Page 578 REGISTERS Px_DIR Address: Table C-15 P x _DIR Reset State: x = 1, 2, 5, 6 Each pin of port x can operate in any of the standard I/O modes of operation: complementary output, open-drain output, or high-impedance input. The port x I/O direction (P x _DIR) register determines the I/O mode for each port x pin.
Page 579 8XC196K x, J x , CA USER’S MANUAL Px_MODE Address: Table C-16 P x _MODE Reset State: x = 1, 2, 5, 6 Each bit in the port x mode (P x _MODE) register determines whether the corresponding pin functions as a standard I/O port pin or is used for a special-function signal.
Page 580 REGISTERS Px_MODE Table C-17. Special-function Signals for Ports 1, 2, 5, 6 Port 1 Port 2 Special-function Signal Special-function Signal P1.0 EPA0/T2CLK P2.0 TXD/PVER P1.1 EPA1 P2.1 RXD/PALE# P1.2 EPA2/T2DIR P2.2 EXTINT/PROG# BREQ# (8XC196K x ) P1.3 EPA3 P2.3 P1.4 EPA4 (8XC196K x ) P2.4 AINC# (87C196CA, 8XC196J x )
Page 581 8XC196K x, J x , CA USER’S MANUAL Px_PIN Address: Table C-18 P x _PIN Reset State: x = 0–6 The port x pin input (P x _PIN) register contains the current state of each port pin, regardless of the pin mode setting.
Page 582 REGISTERS Px_REG Address: Table C-19 P x _REG Reset State: x = 1–6 P x _REG contains data to be driven out by the respective pins. When a port pin is configured as an input, the corresponding bit in P x _REG must be set. The effect of a write to P x _REG is seen on the pins only when the associated pins are configured as standard I/O port pins (P x _MODE.
Page 583 8XC196K x, J x , CA USER’S MANUAL P34_DRV Address: 1FF4H P34_DRV Reset State: The port 3/4 complementary enable (P34_DRV) register controls whether the port is configured as complementary or open-drain outputs. In complementary operation, Ports 3 and 4 are driven high when a one is written to the P x _REG ( x = 3–4) register.
Page 584 REGISTERS PPW (or SP_PPW) no direct access PPW (or SP_PPW) The PPW register is loaded from the external EPROM (locations 14H and 15H) in auto programming mode. The SP_PPW register is loaded from the internal test ROM in serial port programming mode. The default pulse width for serial port programming is longer than required, so you should change the value before beginning to program the device.
Page 585 8XC196K x, J x , CA USER’S MANUAL no direct access The processor status word (PSW) actually consists of two bytes. The high byte is the status word, which is described here; the low byte is the INT_MASK register. The status word contains one bit (PSW.1) that globally enables or disables servicing of all maskable interrupts, one bit (PSW.2) that enables or disables the peripheral transaction server (PTS), and six Boolean flags that reflect the state of a user’s program.
Page 586 REGISTERS no direct access PSW (Continued) The processor status word (PSW) actually consists of two bytes. The high byte is the status word, which is described here; the low byte is the INT_MASK register. The status word contains one bit (PSW.1) that globally enables or disables servicing of all maskable interrupts, one bit (PSW.2) that enables or disables the peripheral transaction server (PTS), and six Boolean flags that reflect the state of a user’s program.
Page 587 8XC196K x USER’S MANUAL PTSSEL Address: PTSSEL Reset State: 0000H The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt requests. Setting a bit selects a PTS microcode routine; clearing a bit selects a standard interrupt service routine.
Page 588 REGISTERS PTSSRV Address: PTSSRV Reset State: 0000H The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corre- sponding PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt. When the end-of-PTS interrupt is called, hardware clears the PTSSRV bit.
Page 589 8XC196K x, J x , CA USER’S MANUAL SBUF_RX Address: 1FB8H SBUF_RX Reset State: The serial port receive buffer (SBUF_RX) register contains data received from the serial port. The serial port receiver is buffered and can begin receiving a second data byte before the first byte is read.
Page 590 REGISTERS SBUF_TX Address: 1FBAH SBUF_TX Reset State: The serial port transmit buffer (SBUF_TX) register contains data that is ready for transmission. In modes 1, 2, and 3, writing to SBUF_TX starts a transmission. In mode 0, writing to SBUF_TX starts a transmission only if the receiver is disabled (SP_CON.3=0).
Page 591 8XC196K x, J x , CA USER’S MANUAL SLP_CMD Address: 1FFAH SLP_CMD Reset State: (8XC196K x ) The slave port comand (SLP_CMD) register accepts commands from the master to the slave. The commands are defined by the device software. The slave can read from and write to this register. The master can only write to it.
Page 592 REGISTERS SLP_CON Address: 1FFBH SLP_CON Reset State: (8XC196K x ) The slave port control (SLP_CON) register is used to configure the slave port. Only the slave can access the register. KQ, KR — — — — SLPL IBEMSK OBFMSK KS, KT —...
Page 593 8XC196K x, J x , CA USER’S MANUAL SLP_STAT Address: 1FF8H SLP_STAT Reset State: (8XC196K x ) The master can read the slave port status (SLP_STAT) register to determine the status of the slave. The slave can read all bits and can write bits 3–7 for general-purpose status information. (The bits are user-defined flags.) If the master attempts to write to SLP_STAT, it actually writes to SLP_CMD.
Page 594 REGISTERS Address: Reset State: XXXXH The system’s stack pointer (SP) can point anywhere in internal or external memory; it must be word aligned and must always be initialized before use. The stack pointer is decremented before a PUSH and incremented after a POP, so the stack pointer should be initialized to two bytes above the highest stack location.
Page 595 8XC196K x, J x , CA USER’S MANUAL SP_BAUD Address: 1FBCH SP_BAUD Reset State: 0000H The serial port baud rate (SP_BAUD) register selects the serial port baud rate and clock source. The most-significant bit selects the clock source. The lower 15 bits represent BAUD_VALUE, an unsigned integer that determines the baud rate.
Page 596 REGISTERS SP_CON Address: 1FBBH SP_CON Reset State: The serial port control (SP_CON) register selects the communications mode and enables or disables the receiver, parity checking, and nine-bit data transmission. CA, J x , KQ, KR — — — KS, KT —...
Page 597 8XC196K x, J x , CA USER’S MANUAL SP_STATUS Address: 1FB9H SP_STATUS Reset State: The serial port status (SP_STATUS) register contains bits that indicate the status of the serial port. RPE/RB8 — — Function Number Mnemonic RPE/RB8 Received Parity Error/Received Bit 8 RPE is set if parity is disabled (SP_CON.2=0) and the ninth data bit received is high.
Page 598 REGISTERS SSIO_BAUD Address: 1FB4H SSIO_BAUD Reset State: The synchronous serial port baud (SSIO_BAUD) register enables and disables the baud-rate generator and selects the SSIO baud rate. During read operations, SSIO_BAUD serves as the down- counter monitor. The down-counter is decremented once every four state times when the baud-rate generator is enabled.
Page 599 8XC196K x, J x , CA USER’S MANUAL SSIOx_BUF (RXD, TXD) Address: Table C-21 SSIO x _BUF (RXD, TXD) Reset State: x = 0–1 The synchronous serial receive buffer x (SSIO x _BUF (RXD)) contains received data. Data is shifted into this register from the SD x pin, with the most-significant bit first.
Page 600 REGISTERS SSIOx_CON Address: Table C-22 SSIO x _CON Reset State: x = 0–1 The synchronous serial control x (SSIO x _CON) registers control the communications mode and handshaking. The two least-significant bits indicate whether an overflow or underflow has occurred and whether the channel is ready to transmit or receive.
Page 601 8XC196K x, J x , CA USER’S MANUAL SSIOx_CON Address: Table C-22 SSIO x _CON (Continued) Reset State: x = 0–1 The synchronous serial control x (SSIO x _CON) registers control the communications mode and handshaking. The two least-significant bits indicate whether an overflow or underflow has occurred and whether the channel is ready to transmit or receive.
Page 602 REGISTERS T1CONTROL Address: 1F98H T1CONTROL Reset State: The timer 1 control (T1CONTROL) register determines the clock source, counting direction, and count rate for timer 1. Function Number Mnemonic Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
Page 603 8XC196K x, J x , CA USER’S MANUAL T2CONTROL Address: 1F9CH T2CONTROL Reset State: The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count rate for timer 2. Function Number Mnemonic Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
Page 604 REGISTERS TIMERx Address: Table C-23 TIMER x Reset State: x = 1–2 The two bytes of the timer x register contain the value of timer x . This register can be written, allowing timer x to be initialized to a value other than zero. Timer Value (high byte) Timer Value (low byte) Function...
Page 605 These bits can be programmed, but cannot be erased. WARNING: These bits can be programmed, but can never be erased. Programming these bits makes dynamic failure analysis impossible. For this reason, devices with programmed UPROM bits cannot be returned to Intel for failure analysis. — — —...
Page 606 REGISTERS WATCHDOG Address: WATCHDOG Reset State: Unless it is cleared every 64K state times, the watchdog timer resets the device. To clear the watchdog timer, send “1EH” followed immediately by “E1H” to location 0AH. Clearing this register the first time enables the watchdog with an initial value of 0000H, which is incremented once every state time.
Page 607 8XC196K x, J x , CA USER’S MANUAL Address: Reset State: The window selection register (WSR) has two functions. One bit enables and disables the bus-hold protocol. The remaining bits select windows. Windows map sections of RAM into the upper section of the lower register file, in 32-, 64-, or 128-byte increments.
Page 608 REGISTERS Table C-24. WSR Settings and Direct Addresses for Windowable SFRs (Continued) 32-Byte Windows 64-Byte Windows 128-Byte Windows (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Memory Register Mnemonic Location Direct Direct Direct Address Address Address CAN_CON (CA) 1E00H 00E0H 00C0H 0080H CAN_EGMSK (CA) 1E08H 00E8H 00C8H 0088H...
Page 609 8XC196K x, J x , CA USER’S MANUAL Table C-24. WSR Settings and Direct Addresses for Windowable SFRs (Continued) 32-Byte Windows 64-Byte Windows 128-Byte Windows (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Memory Register Mnemonic Location Direct Direct Direct Address Address Address CAN_MSG14CON0 (CA) 1EE0H 00E0H 00E0H...
Page 610 REGISTERS Table C-24. WSR Settings and Direct Addresses for Windowable SFRs (Continued) 32-Byte Windows 64-Byte Windows 128-Byte Windows (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Memory Register Mnemonic Location Direct Direct Direct Address Address Address CAN_MSG15DATA0 (CA) 1EF7H 00F7H 00F7H 00F7H CAN_MSG1DATA1 (CA) 1E18H 00F8H 00D8H 0098H...
Page 611 8XC196K x, J x , CA USER’S MANUAL Table C-24. WSR Settings and Direct Addresses for Windowable SFRs (Continued) 32-Byte Windows 64-Byte Windows 128-Byte Windows (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Memory Register Mnemonic Location Direct Direct Direct Address Address Address CAN_MSG1DATA3 (CA) 1E1AH 00FAH 00DAH...
Page 612 REGISTERS Table C-24. WSR Settings and Direct Addresses for Windowable SFRs (Continued) 32-Byte Windows 64-Byte Windows 128-Byte Windows (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Memory Register Mnemonic Location Direct Direct Direct Address Address Address CAN_MSG2DATA5 (CA) 1E2CH 00ECH 00ECH 00ACH CAN_MSG3DATA5 (CA) 1E3CH 00FCH 00FCH 00BCH...
Page 613 8XC196K x, J x , CA USER’S MANUAL Table C-24. WSR Settings and Direct Addresses for Windowable SFRs (Continued) 32-Byte Windows 64-Byte Windows 128-Byte Windows (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Memory Register Mnemonic Location Direct Direct Direct Address Address Address CAN_MSG3DATA7 (CA) 1E3EH 00FEH 00FEH...
Page 614 REGISTERS Table C-24. WSR Settings and Direct Addresses for Windowable SFRs (Continued) 32-Byte Windows 64-Byte Windows 128-Byte Windows (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Memory Register Mnemonic Location Direct Direct Direct Address Address Address CAN_MSG4ID1 (CA) 1E43H 00E3H 00C3H 00C3H CAN_MSG5ID1 (CA) 1E53H 00F3H 00D3H 00D3H...
Page 615 8XC196K x, J x , CA USER’S MANUAL Table C-24. WSR Settings and Direct Addresses for Windowable SFRs (Continued) 32-Byte Windows 64-Byte Windows 128-Byte Windows (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Memory Register Mnemonic Location Direct Direct Direct Address Address Address CAN_MSG5ID3 (CA) 1E55H 00F5H 00D5H...
Page 616 REGISTERS Table C-24. WSR Settings and Direct Addresses for Windowable SFRs (Continued) 32-Byte Windows 64-Byte Windows 128-Byte Windows (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Memory Register Mnemonic Location Direct Direct Direct Address Address Address † EPA4_TIME (K x ) 1F72H 00F2H 00F2H 00F2H EPA5_CON (K x ) 1F74H 00F4H...
Page 617 8XC196K x, J x , CA USER’S MANUAL Table C-24. WSR Settings and Direct Addresses for Windowable SFRs (Continued) 32-Byte Windows 64-Byte Windows 128-Byte Windows (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Memory Register Mnemonic Location Direct Direct Direct Address Address Address SSIO0_BUF 1FB0H 00F0H 00F0H 00B0H...
Page 618 REGISTERS ZERO_REG Address: ZERO_REG Reset State: 0000H The two-byte zero register (ZERO_REG) is always equal to zero. It is useful as a fixed source of the constant zero for comparisons and calculations. ZERO_REG can also be used as the WORD variable in a long-indexed reference.
Page 619 8XC196K x, J x , CA USER’S MANUAL ZERO_REG C-92...
Page 620 Glossary...
Page 622 GLOSSARY This glossary defines acronyms, abbreviations, and terms that have special meaning in this man- ual. (Chapter 1 discusses notational conventions and general terminology.) absolute error The maximum difference between corresponding actual and ideal code transitions. Absolute error accounts for all deviations of an actual A/D converter from an ideal converter.
Page 623 8XC196K x , J x , CA USER’S MANUAL Controller area network. The 8XC196CA’s integrated networking peripheral, similar to Intel’s standalone 82527 CAN serial communications controller, that supports CAN specification 2.0. CCBs Chip configuration bytes. The chip configuration registers (CCRs) are loaded with the contents of the...
Page 624 GLOSSARY code width The voltage change corresponding to the difference between two adjacent code transitions. Code width deviations cause differential nonlinearity and nonlin- earity errors. crosstalk See off-isolation. DC input leakage Leakage current from an analog input pin to ground. deassert The act of making a signal inactive (disabled).
Page 625 8XC196K x , J x , CA USER’S MANUAL feedthrough The attenuation from an input voltage on the selected channel to the A/D output after the sample window closes. The ability of the A/D converter to reject an input on its selected channel after the sample window closes.
Page 626 GLOSSARY interrupt vector A location in special-purpose memory that holds the starting address of an interrupt service routine. See interrupt service routine. linearity errors See differential nonlinearity and nonlinearity. LONG-INTEGER A 32-bit, signed variable with values from –2 through +2 –1.
Page 627 8XC196K x , J x , CA USER’S MANUAL no missing codes An A/D converter has no missing codes if, for every output code, there is a unique input voltage range which produces that code only. Large differential nonlinearity errors can cause the converter to miss codes.
Page 628 GLOSSARY Programmable interrupt controller. The module responsible for handling interrupts that are to be serviced by interrupt service routines that you provide. Also called simply the interrupt controller. prioritized interrupt Any maskable interrupt or nonmaskable NMI. Two of the nonmaskable interrupts (unimplemented opcode and software trap) are not prioritized;...
Page 629 8XC196K x , J x , CA USER’S MANUAL PTS routine The entire microcoded response to multiple PTS interrupt requests. The PTS routine is controlled by the contents of the PTS control block. PTS transfer The movement of a single byte or word from the source memory location to the destination memory location.
Page 630 GLOSSARY sample delay The time period between the time that A/D converter receives the “start conversion” signal and the time that the sample capacitor is connected to the selected channel. sample delay uncertainty The variation in the sample delay. sample time The period of time that the sample window is open.
Page 631 8XC196K x , J x , CA USER’S MANUAL source current Current flowing out of a device from V . Always a negative value. Stack pointer. special interrupt Any of the three nonmaskable interrupts (unimple- mented opcode, software trap, or NMI). special-purpose memory A partition of memory used for storing the interrupt vectors, PTS vectors, chip configuration bytes, and...
Page 632 GLOSSARY transfer function A graph of output code versus input voltage; the characteristic of the A/D converter. transfer function errors Errors inherent in an analog-to-digital conversion process: quantizing error, zero offset error, full-scale error, differential nonlinearity, and nonlinearity. Errors that are hardware-dependent, rather than being inherent in the process itself, include feedthrough, repeatability, channel-to-channel...
Page 633 8XC196K x , J x , CA USER’S MANUAL Glossary-12...
Page 634 Index...
Page 636 INDEX #, defined, 1-3, A-1 idle, powerdown, reset status, B-21, B-22 AD0–AD15, B-9 AD_COMMAND, 11-8, C-80 ADD instruction, A-2, A-7, A-42, A-43, A-48, A/D converter, 2-11, 11-1–11-19 A-54 actual characteristic, 11-17 ADDB instruction, A-2, A-7, A-43, A-44, A-48, and port 0 reads, 11-14 A-54 and PTS, 5-26–5-31 ADDC instruction, A-2, A-7, A-45, A-48, A-54...
Page 637 software protection, 15-19 timing parameters, 15-17 Baud rate Bus-timing modes, 15-30–15-35 SIO port, 7-10–7-12 comparison, 15-31, 15-32 SSIO port, 8-9 mode 0, 15-32 Baud-rate generator mode 1, 15-32 SSIO port, 8-9 mode 2, 15-33 BAUD_VALUE, 7-11, C-68 mode 3, 15-32 BHE#, 15-2, B-10 BUSWIDTH, 15-9, 15-10, 15-23, 16-26, 16-28, during bus hold, 15-17...
Page 638 and BHE#, 6-14 Controlling the clock source and direction, 10-18, 10-19, C-75, C-76 and bus-width, 15-9 and P5.5, 6-14 CPU, 2-4 and P5.6, 6-14 CPVER, 16-12, B-11 and READY, 6-14 Customer service, 1-8 CCBs, 4-3, 13-8, 15-1, 15-4 fetching, 15-4 security-lock bits, 16-30–16-31 Data instructions, A-50, A-57 CCR0, 15-20...
Page 639 EPA0–EPA9, 10-3, B-11 EPA0_TIME, C-88 EA#, 15-3, 16-13, 16-14, B-11 EPA1_CON, 10-21, C-40, C-88 and P5.0, 6-13 EPA1_TIME, C-88 and P5.3, 6-14 EPA2_CON, C-88 and programming modes, 16-14 EPA2_TIME, C-88 idle, powerdown, reset status, B-20, B-22, EPA3_CON, 10-21, C-40, C-88 B-23 EPA3_TIME, C-88 EBR (indirect) instruction, A-2...
Page 640 A/D threshold voltage, 11-6 Hypertext manuals and datasheets, downloading, A/D voltage drop, 11-12 1-10 capacitor size (powerdown circuit), 14-8 programming voltage, 16-16 PWM duty cycle, 5-32 I/O ports PWM frequency, 5-32 unused inputs, 13-2 SIO baud rate, 7-11, C-68 I/O ports‚ See ports‚ SIO port‚ SSIO port FPAL-96, 3-4 IBE flag, 9-5, 9-14, 9-15 Frequency...
Page 641 controller, 2-6, 5-1 JNVT instruction, A-2, A-5, A-22, A-46, A-52, end-of-PTS, 5-19 A-58 inhibiting, 5-8 JST instruction, A-3, A-5, A-22, A-46, A-52, A-58 latency, 5-7–5-10, 5-24 Jump instructions, A-57 calculating, 5-9 conditional, A-5, A-52, A-58 multiplexed, 10-29 unconditional, A-51 priorities, 10-30 JV instruction, A-3, A-5, A-22, A-46, A-52, A-58 pending registers‚...
Page 642 special-purpose memory, 4-3, 16-2 Noise, reducing, 6-2, 6-3, 6-7, 11-3, 11-13, 11-14, Memory protection, 16-3–16-7 13-4, 13-5, 13-6 CCR security-lock bits, 16-18 NOP instruction, 3-11, A-3, A-27, A-47, A-53, UPROM security bits, 16-7 A-59 Memory space, See memory partitions two-byte‚ See SKIP instruction Memory, external, 15-1–15-40 NORML instruction, 3-4, A-3, A-27, A-42, A-53, interface signals, 15-1...
Page 643 Overflow-trap (VT) flag, A-4, A-5, A-11, A-22, Parity, 7-6, 7-7 PBUS, 16-13 A-23 PBUS0–PBUS15, B-15 PC (program counter), 2-4, 2-6 PD bit, 14-4 P0.0–P0.7 Peripherals, internal, 2-8 idle, powerdown, reset status, B-20 Pin diagrams, B-3, B-5, B-7 P0.2–P0.7 PLM-96 idle, powerdown, reset status, B-21, B-22 conventions, 3-9, 3-10, 3-11 P0.4–P0.7 interrupt procedures, 3-11...
Page 644 Port 3 Powerdown mode, 2-11, 2-12, 14-4–14-7 circuitry addressing, 6-15 configuration, 6-18 external, 14-7, 14-8 configuring for slave port, 9-14 disabling, 14-4 idle, powerdown, reset status, B-20, B-21, entering, 14-5 B-22 exiting with EXTINT, 14-6–14-9 operation, 6-16–6-18 exiting with V , 14-5 overview, 6-1 pin status, B-20, B-21, B-22...
Page 645 PTS control block‚ See PTSCB See also windows PTS instructions, A-53, A-59 Register RAM, 4-12, 5-19 PTSCB, 5-1, 5-4, 5-7, 5-8, 5-19, 5-24 and powerdown mode, 14-3, 14-4 memory locations, 4-4 Register-direct addressing, 3-6, 3-9, 4-12 PTSSEL, 5-7, 5-11, 5-19 and register RAM, 4-12 PTSSRV, 5-7, 5-19 and windows, 4-13, 4-23...
Page 646 P6_PIN, 7-3 and CCB fetch, 13-8 and CLKOUT, 13-9 P6_REG, 7-3 considerations, 6-15 and device reset, 13-8, 13-9, 13-10, 15-20 PPW, 16-8, 16-9, 16-35 and ONCE mode, 14-9 PSW, 5-4, 5-15 and powerdown mode, 14-6 PTSCON, 5-21 and programming modes, 16-14 PTSCOUNT, 5-19 idle, powerdown, reset status, B-20, B-22, B-23...
Page 647 Serial I/O port‚ See SIO port half-duplex considerations, 7-7 Serial port programming mode, 16-32–16-43 interrupts, 7-6, 7-8, 7-14 circuit, 16-33 mode 0, 7-4–7-5 defaults, 16-34, 16-35 mode 1, 7-6 functions, 16-32 mode 2, 7-6, 7-7 memory map, 16-34 mode 3, 7-6, 7-7 operation, 16-36 multiprocessor communications, 7-7, 7-8 overrun error, 7-14...
Page 648 modes, 9-8–9-13 block diagram, 8-1 configuring port pins, 8-9 overview, 9-2–9-5 programming enabling interrupts, 8-13 SLP_CON register, 9-14–9-16 handshaking, 8-6, 8-7 programming SFRs, 9-14 configuring, 8-6 selecting data or command and status flow diagram, 8-7 registers, 9-15, C-65 modes, 8-3–8-6 overview, 8-1 SFRs, 9-3 shared memory mode, 9-11–9-13...
Page 649 Timer, watchdog‚ See watchdog timer Timer/counters, 2-10, 10-6, 10-7 , 13-1, B-18 and PWM, 10-14, 10-15, 10-16 and programming modes, 16-14 cascading, 10-7 , 13-1, 14-2, 16-13, B-18 configuring pins, 10-2 and programming modes, 16-14 count rate, 10-7 hardware considerations, 14-7 resolution, 10-7 idle, powerdown, reset status, B-20, B-22, SFRs, 10-3...
Page 650 XCHB instruction, A-2, A-3, A-40, A-42, A-50, A-57 XOR instruction, A-2, A-40, A-44, A-49, A-55 XORB instruction, A-2, A-41, A-44, A-49, A-55 XTAL1, 13-2, B-19 and Miller effect, 13-8 and programming modes, 16-14, 16-32 and SIO baud rate, 7-12 and SSIO baud rate, 8-9 hardware connections, 13-6, 13-7 idle, powerdown, reset status, B-21, B-22, B-23...

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