Intel 8XC196NP Manuals

Manuals and User Guides for Intel 8XC196NP. We have 1 Intel 8XC196NP manual available for free PDF download: User Manual

Intel 8XC196NP User Manual (471 pages)

Brand: Intel | Category: Microcontrollers | Size: 2.78 MB

Table of Contents
4
Guide to this Manual
18
Manual Contents
20
Notational Conventions and Terminology
22
Related Documents
24
Electronic Support Systems
27
Faxback Service
27
Bulletin Board System (BBS)
28
How to Find Ap BUILDER Software and Hypertext Documents on the BBS
29
Compuserve Forums
29
World Wide Web
30
Technical Support
30
Product Literature
30
Architectural Overview
32
Typical Applications
34
Device Features
35
Block Diagram
35
CPU Control
36
Register File
36
Register Arithmetic-Logic Unit (RALU)
37
Code Execution
37
Instruction Format
38
Memory Controller
38
Multiply-Accumulate (80C196NU Only)
39
Interrupt Service
39
Internal Timing
40
Internal Peripherals
44
I/O Ports
44
Serial I/O (SIO) Port
44
Event Processor Array (EPA) and Timer/Counters
44
Pulse-Width Modulator (PWM)
45
Special Operating Modes
45
Reducing Power Consumption
45
Testing the Printed Circuit Board
46
Design Considerations for 80C196Np to 80C196Nu Conversions
46
Advanced Math Features
48
Enhanced Multiplication Instructions
50
Operating Modes
51
Saturation Mode
51
Fractional Mode
52
Accumulator Control and Status Register (Acc_Stat)
54
Programming Considerations
56
Overview of the Instruction Set
58
BIT Operands
59
BYTE Operands
59
SHORT-INTEGER Operands
59
WORD Operands
60
INTEGER Operands
60
DOUBLE-WORD Operands
60
LONG-INTEGER Operands
61
QUAD-WORD Operands
61
Converting Operands
61
Conditional Jumps
61
Floating Point Operations
62
Extended Instructions
62
Addressing Modes
63
Direct Addressing
64
Immediate Addressing
64
Indirect Addressing
64
Extended Indirect Addressing
65
Indirect Addressing with Autoincrement
65
Extended Indirect Addressing with Autoincrement
65
Indirect Addressing with the Stack Pointer
66
Indexed Addressing
66
Short-Indexed Addressing
66
Long-Indexed Addressing
66
Extended Indexed Addressing
67
Zero-Indexed Addressing
67
Extended Zero-Indexed Addressing
67
Assembly Language Addressing Mode Selections
68
Direct Addressing
68
Indexed Addressing
68
Extended Addressing
68
Design Considerations for 1-Mbyte Devices
68
Software Standards and Conventions
68
Using Registers
69
Addressing 32-Bit Operands
69
Addressing 64-Bit Operands
69
Linking Subroutines
70
Software Protection Features and Guidelines
71
Memory Partitions
72
Memory Map Overview
74
Memory Partitions
74
External Memory
78
Program and Special-Purpose Memory
78
Program Memory in
78
Special-Purpose Memory
79
Reserved Memory Locations
80
Interrupt and PTS Vectors
80
Chip Configuration Bytes
80
Peripheral Special-Function Registers (Sfrs)
80
Register File
82
General-Purpose Register RAM
83
Stack Pointer (SP)
83
CPU Special-Function Registers (Sfrs)
85
Windowing
86
Selecting a Window
87
Addressing a Location through a Window
89
32-Byte Windowing Example
91
Unsupported Locations Windowing Example (8XC196NP Only)
92
Using the Linker Locator to Set up a Window
92
Windowing and Addressing Modes
94
Remapping Internal Rom (83C196Np Only)
95
Fetching Code and Data in the 1-Mbyte and 64-Kbyte Modes
96
Fetching Instructions
96
Accessing Data
96
Code Fetches in the 1-Mbyte Mode
98
Code Fetches in the 64-Kbyte Mode
98
Data Fetches in the 1-Mbyte and 64-Kbyte Modes
99
Memory Configuration Examples
100
Example 1: Using the 64-Kbyte Mode
100
Example 2: a 64-Kbyte System with Additional Data Storage
102
Example 3: Using 1-Mbyte Mode
104
Standard and Pts Interrupts
106
Overview of Interrupts
108
Interrupt Signals and Registers
110
Interrupt Sources and Priorities
111
Special Interrupts
111
Unimplemented Opcode
112
Software Trap
112
Nmi
113
External Interrupt Pins
113
Multiplexed Interrupt Sources
113
End-Of-PTS Interrupts
113
Interrupt Latency
114
Situations that Increase Interrupt Latency
114
Calculating Latency
115
Standard Interrupt Latency
115
PTS Interrupt Latency
116
Programming the Interrupts
117
Programming Considerations for Multiplexed Interrupts
118
Modifying Interrupt Priorities
120
Determining the Source of an Interrupt
122
Initializing the Pts Control Blocks
124
Specifying the PTS Count
125
Selecting the PTS Mode
126
Single Transfer Mode
127
Block Transfer Mode
130
PWM Modes
133
PWM Toggle Mode Example
134
PWM Remap Mode Example
139
I/O Ports
144
I/O Ports Overview
146
Bidirectional Port Operation
148
Bidirectional Port Pin Configurations
152
Bidirectional Port Pin Configuration Example
153
Bidirectional Port Considerations
154
Design Considerations for External Interrupt Inputs
156
Eport
156
EPORT Operation
157
Reset
159
Output Enable
159
Complementary Output Mode
159
Open-Drain Output Mode
159
Configuring EPORT Pins
162
Configuring EPORT Pins for Extended-Address Functions
162
Configuring EPORT Pins for I/O
162
EPORT Considerations
163
EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold
163
EP_REG Settings for Pins Configured as Extended-Address Signals
163
EPORT Status During Instruction Execution
163
Design Considerations
164
Serial I/O (Sio) Port
166
Serial I/O (Sio) Port Functional Overview
168
Serial I/O Port Signals and Registers
169
Serial Port Modes
171
Synchronous Mode (Mode 0)
171
Asynchronous Modes (Modes 1, 2, and 3)
172
Mode 1
173
Mode 2
174
Mode 2 and 3 Timings
174
Multiprocessor Communications
175
Programming the Serial Port
175
Configuring the Serial Port Pins
175
Programming the Control Register
175
Programming the Baud Rate and Clock Source
175
Enabling the Serial Port Interrupts
180
Determining Serial Port Status
180
Pulse-Width Modulator
184
Pwm Functional Overview
186
Pwm Signals and Registers
187
Pwm Operation
188
Programming the Frequency and Period
190
Programming the Duty Cycle
192
Sample Calculations
194
Enabling the PWM Outputs
194
Generating Analog Outputs
194
Event Processor Array (Epa)
196
Epa Functional Overview
198
Epa and Timer/Counter Signals and Registers
199
Timer/Counter Functional Overview
202
Cascade Mode (Timer 2 Only)
203
Quadrature Clocking Mode
203
Epa Channel Functional Overview
205
Operating in Capture Mode
206
EPA Overruns
208
Preventing EPA Overruns
209
Operating in Compare Mode
209
Generating a Low-Speed PWM Output
209
Generating a Medium-Speed PWM Output
210
Generating a High-Speed PWM Output
211
Generating the Highest-Speed PWM Output
212
Programming the Epa and Timer/Counters
212
Configuring the EPA and Timer/Counter Port Pins
212
Programming the Timers
212
Programming the Capture/Compare Channels
215
Enabling the Epa Interrupts
219
Determining Event Status
219
Using Software to Service the Multiplexed Overrun Interrupts
220
Programming Examples for Epa Channels
221
EPA Compare Event Program
221
EPA Capture Event Program
222
EPA PWM Output Program
223
Minimum Hardware Considerations
226
Minimum Connections
228
Unused Inputs
229
I/O Port Pin Connections
229
Applying and Removing Power
231
Noise Protection Tips
231
The On-Chip Oscillator Circuitry
232
Using an External Clock Source
234
Resetting the Device
235
Generating an External Reset
236
Issuing the Reset (RST) Instruction
238
Issuing an Illegal IDLPD Key Operand
238
Special Operating Modes
240
Special Operating Mode Signals and Registers
242
Reducing Power Consumption
244
Idle Mode
246
Standby Mode (80C196Nu Only)
247
Enabling and Disabling Standby Mode
247
Entering Standby Mode
247
Exiting Standby Mode
248
Powerdown Mode
248
Enabling and Disabling Powerdown Mode
248
Entering Powerdown Mode
248
Exiting Powerdown Mode
249
Generating a Hardware Reset
249
Asserting an External Interrupt Signal
249
Selecting C
251
Once Mode
253
Reserved Test Modes (80C196Nu Only)
253
Interfacing with External Memory
256
Internal and External Addresses
258
External Memory Interface Signals
259
The Chip-Select Unit
262
Defining Chip-Select Address Ranges
264
Controlling Wait States, Bus Width, and Bus Multiplexing
267
Chip-Select Unit Initial Conditions
268
Initializing the Chip-Select Registers
268
Example of a Chip-Select Setup
269
Chip Configuration Registers and Chip Configuration Bytes
271
Bus Width and Multiplexing
275
A 16-Bit Example System
278
16-Bit Bus Timings
279
8-Bit Bus Timings
281
Comparison of Multiplexed and Demultiplexed Buses
283
Wait States (Ready Control)
283
Bus-Hold Protocol
287
Enabling the Bus-Hold Protocol
289
Disabling the Bus-Hold Protocol
289
Hold Latency
289
Regaining Bus Control
290
Write-Control Modes
290
System Bus Ac Timing Specifications
293
Deferred Bus-Cycle Mode (80C196NU Only)
297
Explanation of AC Symbols
299
AC Timing Definitions
299

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