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8XC196K x, J x , CA USER'S MANUAL
CCR0
CCR0 (Continued)
The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal
memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus
width.
7
LOC1
LOC0
Bit
Bit
Number
Mnemonic
1
BW0
0
PD
C-30
IRC1
IRC0
Buswidth Control
This bit, along with the BW1 bit (CCR1.2), selects the bus width.
BW1 BW0
0
0
illegal
0
1
16-bit only
1
0
8-bit only
1
1
BUSWIDTH pin controlled
†
This mode is unavailable on the 87C196CA, J x devices. The
BUSWIDTH pin is not implemented.
Powerdown Enable
Controls whether the IDLPD #2 instruction causes the device to enter
powerdown mode. Clearing this bit at reset can prevent accidental entry
into powerdown mode.
1 = enable powerdown mode
0 = disable powerdown mode
Address:
Reset State:
ALE
WR
Function
†
2018H
XXH
0
BW0
PD
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