Table of Contents
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Overflow-trap (VT) flag, A-4, A-5, A-11, A-22,
A-23
P
P0.0–P0.7
idle, powerdown, reset status, B-20
P0.2–P0.7
idle, powerdown, reset status, B-21, B-22
P0.4–P0.7
and programming modes, 16-14
P0_PIN, C-89
P1.0–P1.3, B-13
idle, powerdown, reset status, B-21
P1.0–P1.7, B-13
idle, powerdown, reset status, B-20, B-22
P1_DIR, C-89
P1_MODE, C-89
P1_PIN, C-89
P1_REG, C-89
P2.0–P2.7, B-14
P2.2 considerations, 14-7
P2.7 reset status, 6-7
P2_DIR, C-89
P2_MODE, C-89
P2_PIN, C-89
P2_REG, C-89
P3.0–P3.7, B-14
idle, powerdown, reset status, B-20, B-21,
B-22
See also port 3
P4.0–P4.7, B-14
idle, powerdown, reset status, B-20, B-21,
B-22
See also port 4
P5.0–P5.7, B-14
idle, powerdown, reset status, B-20, B-21,
B-23
P6.0–P6.7, B-15
idle, powerdown, reset status, B-20, B-21,
B-23
P6_DIR, C-89
P6_MODE, C-89
P6_PIN, C-89
P6_REG, C-89
PACT#, B-15
PALE#, 16-8, 16-11, 16-12, B-15
Parameters, passing to subroutines, 3-10
Index-8
Parity, 7-6, 7-7
PBUS, 16-13
PBUS0–PBUS15, B-15
PC (program counter), 2-4, 2-6
PD bit, 14-4
Peripherals, internal, 2-8
Pin diagrams, B-3, B-5, B-7
PLM-96
conventions, 3-9, 3-10, 3-11
interrupt procedures, 3-11
PMODE, 16-11, 16-14
and programming modes, 16-14
PMODE0–PMODE3, B-15
POP instruction, A-3, A-28, A-46, A-50, A-56
POPA instruction, A-2, A-29, A-47, A-50, A-56
POPF instruction, A-2, A-29, A-47, A-50, A-56
Port 0, 6-1, 6-2
considerations, 6-3, 11-14, 13-5
idle, reset, powerdown status, B-20
initializing, 6-10
input only pins, 6-2
overview, 6-1
pin configuration
example, 6-11
structure, 6-3
Port 1, B-13
considerations, 6-12
idle, powerdown, reset status, B-20, B-21,
B-22
initializing, 6-10
input buffer, 6-7
logic tables, 6-9
operation, 6-4, 6-9
overview, 6-1
pin configuration, 6-10, 6-12
example, 6-11
SFRs, 6-5, 6-6, 10-4, 10-5
structure, 6-8
Port 2, 14-2, B-14
considerations, 6-12
initializing, 6-10
logic tables, 6-9
operation, 6-4, 6-9
overview, 6-1
pin configuration, 6-10, 6-12
example, 6-11
SFRs, 6-5, 6-6, 14-2
structure, 6-8
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