Generating An External Reset - Intel 8XC196K Series User Manual

8XC196K x , J x , CA USER'S MANUAL
Internal
Reset
Signal
RST Instruction
WDT Overflow
IDLPD Invalid Key
USFR.0
OFD
(F OSC < 100 kHz)
† See the datasheet for minimum and maximum R

13.5.1 Generating an External Reset

To reset the device, hold the RESET# pin low for at least one state time after the power supply is
within tolerance and the oscillator has stabilized. When RESET# is first asserted, the device turns
on a pull-down transistor (Q1) for 16 state times. This enables the RESET# signal to function as
the system reset.
The simplest way to reset the device is to insert a capacitor between the RESET# pin and V
shown in Figure 13-9. The device has an internal pull-up (R
remain asserted for at least one state time after V
erating conditions specified in the datasheet. A capacitor of 4.7 µF or greater should provide suf-
ficient reset time, as long as V
13-10
Reset State
Machine
Trigger
Count Complete
CLR
Q
SET
values.
RST
Figure 13-8. Internal Reset Circuitry
CC
rises quickly.
CC
Internal
V CC
Clock
†
R RST
~200 Ω
Q1
) (Figure 13-8). RESET# should
RST
and XTAL1 have stabilized and met the op-
External
RESET#
A0034-02
, as
SS