Modifying Interrupt Priorities - Intel 8XC196K Series User Manual

Table of Contents

8XC196K x , J x , CA USER'S MANUAL

The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupts. (The EI

and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can be read

from or written to as a byte register. PUSHA saves this register on the stack and POPA restores it.

Setting this bit enables the corresponding interrupt.

The standard interrupt vector locations are as follows:

Bit Mnemonic Interrupt

Bit 5 is reserved on the 8XC196J x , K x devices and bit 0 is reserved on the 87C196CA, 8XC196J x

devices. For compatibility with future devices, always write zeros to these bits.

NMI is always enabled. This nonfunctional mask bit exists for design symmetry with the

INT_PEND1 register. Always write zero to this bit.

Figure 5-6. Interrupt Mask 1 (INT_MASK1) Register

Modifying Interrupt Priorities

The software can modify the default priorities of maskable interrupts by controlling the interrupt

mask registers (INT_MASK and INT_MASK1). For example, you can specify which interrupts,

if any, can interrupt an interrupt service routine. The following code shows one way to prevent

all interrupts, except EXTINT (priority 14), from interrupting an SIO receive interrupt service

routine (priority12).

Nonmaskable Interrupt

CAN Peripheral

SIO Transmit

SSIO 1 Transfer

SSIO 0 Transfer

Slave Port Command Buffer Full

Reset State:

Standard Vector