Intel 8XC196K Series User Manual page 153

8XC196K x , J x , CA USER'S MANUAL
P5.3/RD#
P5.4/SLPINT
P5.5/BHE#/WRH#
P5.6/READY
P5.7/BUSWIDTH
P6.0–P6.7
6-14
If EA# is high on reset (internal access), the pin is weakly held high
until your software writes to P5_MODE. If EA# is low on reset
(external access), RD# is activated as a system control pin and the
pin becomes a true complementary output.
8XC196Kx Only: This pin is weakly held high until your software
writes to P5_MODE. P5.4/SLPINT is the enable pin for ONCE mode
in certain 8XC196Kx devices (see Chapter 14, "Special Operating
Modes") and one of the enable pins for Intel-reserved test modes.
Because a low input during reset could cause the device to enter
ONCE mode or a reserved test mode, exercise caution if you use this
pin for input. Be certain that your system meets the V
(listed in the datasheet) during reset to prevent inadvertent entry into
ONCE mode or a test mode.
This pin is weakly held high until the CCB fetch is completed. At
that time, the state of this pin depends on the value of the BW0 bit of
the CCRs. If BW0 is clear, the pin remains weakly held high until
your software writes to P5_MODE. If BW0 is set, BHE# is activated
as a system control pin and the pin becomes a true complementary
output.
8XC196CA, Kx Only: This pin remains weakly held high until the
CCB fetch is completed. At that time, the state of this pin depends on
the value of the IRC0–IRC2 bits of the CCRs. If IRC0–IRC2 are all
set (111B), READY is activated as a system control pin. This
prevents the insertion of infinite wait states upon the first access to
external memory. For any other values of IRC0–IRC2, the pin is
configured as I/O upon reset.
If IRC0–IRC2 of the CCB are all set (activating READY as a
system control pin) and P5_MODE.6 is cleared (configuring
the pin as I/O), an external memory access may cause the
processor to lock up.
8XC196Kx Only: This pin remains weakly held high until your
software writes configuration data into P5_MODE.
After reset, your software must configure the device to match the
external system. This is accomplished by writing appropriate config-
uration data into P6_MODE. Writing to P6_MODE not only
configures the pins but also turns off the transistor that weakly holds
the pins high (Q4 in Figure 6-2 on page 6-8). For this reason, even if
port 6 is to be used as it is configured at reset, you should still write
data into P6_MODE.
specification
IH
NOTE