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CCR0
The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal
memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus
width.
7
LOC1
LOC0
Bit
Bit
Number
Mnemonic
7:6
LOC1:0
5:4
IRC1:0
3
ALE
2
WR
IRC1
IRC0
Lock Bits
Determine the programming protection scheme for internal memory.
LOC1 LOC0
0
0
read and write protect
0
1
read protect only
1
0
write protect only
1
1
no protection
Internal Ready Control
These two bits, along with IRC2 (CCR1.1), limit the number of wait states
that can be inserted while the READY pin is held low. Wait states are
inserted into the bus cycle either until the READY pin is pulled high or
until this internal number is reached.
IRC2 IRC1 IRC0
0
0
0
zero wait states
0
X
1
illegal
0
1
X
illegal
1
0
0
one wait state
1
0
1
two wait states
1
1
0
three wait states
1
1
1
infinite
†
This mode is unavailable on the 8XC196J x device. On this device, the
READY pin is not implemented. Therefore, the number of wait states
inserted into the bus cycle is determined only by the IRC2:0 bit settings.
Address Valid Strobe and Write Strobe
These bits define which bus-control signals will be generated during
external read and write cycles.
ALE WR
0
0
address valid with write strobe mode
(ADV#, RD#, WRL#, WRH#)
0
1
address valid strobe mode
(ADV#, RD#, WR#, BHE#)
1
0
write strobe mode
(ALE, RD#, WRL#, WRH#)
1
1
standard bus-control mode
(ALE, RD#, WR#, BHE#)
†
On the 8XC196J x device, the BHE#/WRH# pin is not implemented.
Address:
Reset State:
ALE
WR
Function
†
†
†
†
†
REGISTERS
CCR0
2018H
XXH
0
BW0
PD
C-29
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