Intel 8XC196K Series User Manual page 601

8XC196K x, J x , CA USER'S MANUAL
SSIOx_CON
SSIO x _CON (Continued)
x = 0–1
The synchronous serial control x (SSIO x _CON) registers control the communications mode and
handshaking. The two least-significant bits indicate whether an overflow or underflow has occurred
and whether the channel is ready to transmit or receive.
7
M/S# T/R#
Bit Bit
Number Mnemonic
1 OUF
0 TBS
†
The M/S# and T/R# bits specify four possible configurations: master transmitter, master receiver,
slave transmitter, or slave receiver.
Table C-22. SSIO x _CON Addresses and Reset Values
SSIO0_CON
SSIO1_CON
C-74
TRT THS
Overflow/Underflow Flag
Indicates whether an overflow or underflow has occurred. An attempt to
access SSIO x _BUF during a byte transfer sets this bit.
For the master (M/S# = 1)
0 = no overflow or underflow has occurred
1 = the core attempted to access SSIO x _BUF during the current transfer
For the slave (M/S# = 0)
0 = no overflow or underflow has occurred
1 = the core attempted to access SSIO x _BUF during the current transfer
or the master attempted to clock data into or out of the slave's
SSIO x _BUF before the buffer was available
Transceiver Buffer Status
Indicates the status of the channel's SSIO x _BUF.
For the transmitter (T/R# =1)
0 = SSIO x _BUF is full; waiting to transmit
1 = SSIO x _BUF is empty; buffer available
For the receiver (T/R# = 0)
0 = SSIO x _BUF is empty; waiting to receive
1 = SSIO x _BUF is full; data available
Register
STE ATR
Function
Address Reset Value
1FB1H
1FB3H
Address: Table C-22
Reset State:
0
OUF TBS
00H
00H