Intel 8XC196K Series User Manual page 573

Table of Contents

8XC196K x, J x , CA USER'S MANUAL

The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupts. (The EI

and DI instructions enable and disable servicing of all maskable interrupts.). INT_MASK is the low

byte of the program status word (PSW). PUSHF or PUSHA saves the contents of this register onto the

stack and then clears this register. Interrupt calls cannot occur immediately following this instruction.

POPF or POPA restores it.

Setting this bit enables the corresponding interrupt.

The standard interrupt vector locations are as follows:

Bit Mnemonic Interrupt

EPA 4–9 capture/compare channel events, EPA 0–1 compare channel events, EPA 0–

9 capture/compare overruns, and timer overflows can generate this multiplexed interrupt.

The EPA mask and pending registers decode the EPA x interrupt. Write the EPA mask

registers (EPA_MASK and EPA_MASK1) to enable the interrupt sources; read the EPA

pending registers (EPA_PEND and EPA_PEND1) to determine which source caused the

Bits 6–7 are reserved on the 87C196CA and 8XC196J x devices. For compatibility with future

devices, write zeros to these bits.

Slave Port Input Buffer Full

Slave Port Output Buffer Empty

A/D Conversion Complete

EPA Capture/Compare Channel 0

EPA Capture/Compare Channel 1

EPA Capture/Compare Channel 2

EPA Capture/Compare Channel 3

Multiplexed EPA

Reset State:

Standard Vector