Direct Addressing; Immediate Addressing; Indirect Addressing - Intel 8XC196K Series User Manual

8XC196K x , J x , CA USER'S MANUAL
Temporary Register
AX
BX
CX
DX
3.2.1

Direct Addressing

Direct addressing directly accesses a location in the 256-byte lower register file, without involv-
ing the memory controller. Windowing allows you to remap other sections of memory into the
lower register file for register-direct access (see Chapter 4, "Memory Partitions," for details). You
specify the registers as operands within the instruction. The register addresses must conform to
the alignment rules for the operand type. Depending on the instruction, up to three registers can
take part in a calculation. The following instructions use register-direct addressing:
ADD AX,BX,CX
ADDB AL,BL,CL
MUL AX,BX
INCB CL
3.2.2

Immediate Addressing

Immediate addressing mode accepts one immediate value as an operand in the instruction. You
specify an immediate value by preceding it with a number symbol (#). An instruction can contain
only one immediate value; the remaining operands must be register-direct references. The follow-
ing instructions use immediate addressing:
ADD AX,#340
PUSH #1234H
DIVB AX,#10
3.2.3

Indirect Addressing

The indirect addressing mode accesses an operand by obtaining its address from a WORD regis-
ter in the lower register file. You specify the register containing the indirect address by enclosing
it in square brackets ([ ]). The indirect address can refer to any location within the address space,
including the register file. The register that contains the indirect address must be word-aligned,
and the indirect address must conform to the rules for the operand type. An instruction can contain
only one indirect reference; any remaining operands must be register-direct references. The fol-
lowing instructions use indirect addressing:
LD AX,[BX]
3-6
Table 3-3. Definition of Temporary Registers
word-aligned 16-bit register; AH is the high byte of AX and AL is the low byte
word-aligned 16-bit register; BH is the high byte of BX and BL is the low byte
word-aligned 16-bit register; CH is the high byte of CX and CL is the low byte
word-aligned 16-bit register; DH is the high byte of DX and DL is the low byte
; AX ← BX + CX
; AL ← BL + CL
; AX ← AX * BX
; CL ← CL + 1
; AX ← AX + 340
; SP ← SP - 2
; MEM_WORD(SP) ← 1234H
; AL ← AX/10
; AH ← AX MOD 10
; AX ← MEM_WORD(BX)
Description