Device Features; Block Diagram - Intel 8XC196K Series User Manual

8XC196K x , J x , CA USER'S MANUAL
2.2

DEVICE FEATURES

Table 2-1 lists the features of each member of the 8XC196Kx family.
Table 2-1. Features of the 8XC196K x, J x , CA Product Family
OTPROM/
Device Pins
(3)
8XC196JV 52
8XC196KT 68
(3)
8XC196JT 52
(4)
87C196CA 68
(3)
8XC196KS 68
8XC196KR 68
8XC196JR 52
8XC196KQ 68
8XC196JQ 52
NOTES:
1. Optional. The second character of the device name indicates the presence and type of nonvolatile
memory. 80C196 xx = none; 83C196 xx = ROM; 87C196 xx = OTPROM or EPROM.
2. Register RAM amounts include the 24 bytes allocated to core SFRs and the stack pointer.
3. The 8XC196JT, JV, and KS are offered in automotive temperature ranges only. The 87C196CA,
8XC196JQ, JR, KQ, KR, and KT are offered in both automotive and commercial temperature ranges.
4. The 87C196CA also has an on-chip networking peripheral that supports CAN specification 2.0.
2.3

BLOCK DIAGRAM

Figure 2-1 shows the major blocks within the device. The core of the device (Figure 2-2) consists
of the central processing unit (CPU) and memory controller. The CPU contains the register file
and the register arithmetic-logic unit (RALU). The CPU connects to both the memory controller
and an interrupt controller via a 16-bit internal bus. An extension of this bus connects the CPU to
the internal peripheral modules. In addition, an 8-bit internal bus transfers instruction bytes from
the memory controller to the instruction register in the RALU.
2-2
Register
EPROM/
(2)
RAM Data RAM
(1)
ROM
48 K 1536
32 K 1024
32 K 1024
32 K 1024
24 K 1024
16 K 512
16 K 512
12 K 384
12 K 384
Code/ I/O EPA
Pins Pins
Ports
512 56 6
512 56 10
512 41 6
256 51 6
256 56 10
256 56 10
256 41 6
128 56 10
128 41 6
SIO/ External
A/D
SSIO Interrupt
Channels
Pins
3 6
3 8
3 6
3 6
3 8
3 8
3 6
3 8
3 6
1
2
1
2
2
2
1
2
1