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Intel Agilex User Manual

Intel Agilex User Manual

General purpose i/o and lvds serdes
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  • Page 1 ® ™ Intel Agilex General Purpose I/O and LVDS SERDES User Guide Subscribe UG-20214 | 2019.04.02 Send Feedback Latest document on the web: HTML...

  • Page 2: Table Of Contents

    2.1.1. Supported I/O Standards................8 2.1.2. Intel Agilex I/O Buffer Behavior..............10 2.1.3. I/O Standards Restrictions and Implementation Guidelines......10 2.2. Programmable I/O Element (IOE) Features in Intel Agilex Devices......11 2.2.1. Programmable Output Slew Rate Control.............15 2.2.2. Programmable IOE Delay................15 2.2.3.
  • Page 3 5.6.2. Pin Placement for Differential Channels............54 5.6.3. SERDES Pin Pairs for Soft-CDR Mode............54 6. Documentation Related to the Intel Agilex General Purpose I/O and LVDS SERDES User Guide....................... 55 7. Document Revision History for the Intel Agilex General Purpose I/O and LVDS SERDES User Guide....................

  • Page 4: Intel ® Agilex ™ General Purpose I/O And Lvds Serdes Overview

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 5: Package Selection And I/O Vertical Migration Support

    AGF 014 AGF 022 AGF 027 AGI 022 I-Series AGI 027 1.3. I/O Banks There are three types of I/O banks available in the Intel Agilex I/O interface system: • GPIO banks • HPS I/O bank • SDM I/O bank In each GPIO bank, there are two sub-banks.
  • Page 6 ® ™ 1. Intel Agilex General Purpose I/O and LVDS SERDES Overview UG-20214 | 2019.04.02 In each sub-bank, there are four I/O lanes with 12 I/O pins in each lane that make up a total of 48 single-ended I/O pins or 24 true differential I/O pairs per sub-bank. Each...
  • Page 7 General Purpose I/O and LVDS SERDES Overview UG-20214 | 2019.04.02 Figure 2. Intel Agilex I/O Bank Structure (Bottom View) This diagram shows the I/O bank structure of Intel Agilex AGF 012 and AGF 014 devices. I/O Center I/O PLL I/O VR...

  • Page 8: Intel Agilex I/O Features And Usage

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 9 The 1.5 V True Differential Signaling I/O standard is compatible with the LVDS, RSDS, Mini-LVDS, and LVPECL standards at lower signal swing. Refer to Intel Agilex Device Data Sheet for the electrical specifications of the 1.5 V True Differential Signaling I/O standard.

  • Page 10: Intel Agilex I/O Buffer Behavior

    VCCIO_PIO Input signals of an I/O pin at any point should not exceed the maximum DC input voltage specification as specified in the Intel Agilex Device Data Sheet. 2.1.3. I/O Standards Restrictions and Implementation Guidelines Observe the following I/O standard restrictions and implementation guidelines to ensure the success of your design.

  • Page 11: Programmable I/O Element (Ioe) Features In Intel Agilex Devices

    Agilex Device Data Sheet. Analyze the electrical specification requirement to implement your true differential receiver. Implement DC coupling when the signal swing and offset voltage requirement is bounded within the Intel Agilex 1.5 V True Differential Signaling standard specification. Otherwise, implement AC coupling and external bias circuitry.
  • Page 12 2. Intel Agilex I/O Features and Usage UG-20214 | 2019.04.02 Programmable IOE Feature Standard Slew Rate Open-Drain Bus-Hold Weak Pull- Pre- De-Emphasis Differential Control Delay Output up Resistor Emphasis Output Voltage • constant impedance • Medium constant impedance • High...
  • Page 13 Constant • Medium sheet impedance high (Default) • High Table 4. Programmable IOE Feature Settings for Intel Agilex HPS I/O Bank I/O Standard Programmable IOE Feature Current Strength Slew Rate Weak Pull-up/ Schmitt Open Drain Pull-down Trigger/TTL Input 1.8 V LVCMOS •...
  • Page 14 • Weak pull- down with 50 kOhm resistor • Weak pull- down with 80 kOhm resistor Table 5. Intel Agilex Configuration Pin I/O Standards and Features Configuration Pin Location Direction I/O Standard Drive Weak Pull-Up/Pull- Function Strength Down...

  • Page 15: Programmable Output Slew Rate Control

    Intel Agilex Data Sheet 2.2.3. Programmable Open-Drain Output Intel Agilex devices support open drain output on 1.2 V LVCMOS I/O standard. The programmable open-drain output provides a high-impedance state on output when logic to the output buffer is high. If logic to the output buffer is low, output is low.

  • Page 16: Programmable Bus Hold

    If you enable the bus-hold feature, you cannot use the programmable pull-up option. 2.2.5. Programmable Pull-Up Resistor Intel Agilex devices support programmable pull up resistor on 1.2 V LVCMOS I/O. Each I/O pin provides an optional programmable pull-up resistor during user mode.

  • Page 17: Programmable De-Emphasis

    2. Intel Agilex I/O Features and Usage UG-20214 | 2019.04.02 unlike the overshoot caused by signal reflection. The amount of pre-emphasis required depends on the attenuation of the high-frequency component along the transmission line. Figure 3. Programmable Pre-Emphasis This figure shows the true differential output with pre-emphasis.

  • Page 18: Programmable Differential Output Voltage

    2. Intel Agilex I/O Features and Usage UG-20214 | 2019.04.02 Figure 4. Programmable De-emphasis This figure shows the SSTL and HSTL standards with de-emphasis enabled. 1 UI HIGH VCCIO/2 HIGH 2.2.8. Programmable Differential Output Voltage The programmable V settings allow you to adjust the output eye opening to optimize the trace length and power consumption.

  • Page 19: Intel Agilex I/O Termination

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 20: External I/O Termination

    50 Ω 3.1.2. 1.5 V True Differential Signaling I/O Standard OCT Termination All I/O pins and dedicated clock input pins in Intel Agilex devices support on-chip differential termination, R OCT. The Intel Agilex devices provide a 100 ±40 Ω, on- chip differential termination option on each differential receiver channel for 1.5 V True...

  • Page 21: Single-Ended I/O Termination In Intel Agilex Devices

    OCT maintains signal quality, saves board space, and reduces external component costs. Figure 10. and R This figure shows the single-ended termination schemes supported in Intel Agilex devices. R and R dynamic parallel terminations and are enabled only if the device is receiving. In bidirectional applications, R and R are automatically switched on when the device is receiving and switched off when the device is driving.
  • Page 22 3. Intel Agilex I/O Termination UG-20214 | 2019.04.02 Table 6. OCT Schemes Supported in Intel Agilex Devices Direction OCT Schemes Output OCT with calibration OCT without calibration Input OCT with calibration Bidirectional Dynamic R and R The Intel Agilex devices support R OCT with and without calibration for single-ended and voltage-referenced I/O standards.
  • Page 23 3. Intel Agilex I/O Termination UG-20214 | 2019.04.02 Figure 12. OCT with Calibration This figure shows the R as the intrinsic impedance of the output transistors. Driver Receiving Series Termination Device CCIO = 50 Ω Table 7. Selectable I/O Standards for R...
  • Page 24 3. Intel Agilex I/O Termination UG-20214 | 2019.04.02 Transmitter Receiving Device CCIO 2 × R = 50 Ω 2 × R Table 8. Selectable I/O Standards for R OCT With Calibration This table lists the output termination settings for calibrated OCT on different I/O standards.

  • Page 25: Oct Calibration Block

    3. Intel Agilex I/O Termination UG-20214 | 2019.04.02 Figure 13. Dynamic R OCT in Intel Agilex Devices V CCIO V CCIO Transmitter Receiver 100 Ω 2 x R Z 0 = 50 Ω 100 Ω 2 x R 50 Ω...

  • Page 26: Single-Ended I/O Standards External Termination

    (VTT). The reference voltage of the receiving device tracks the termination voltage of the transmitting device. Intel recommends that you use OCT with these I/O standards to save board space and cost. OCT reduces the number of external termination resistors used.
  • Page 27 3. Intel Agilex I/O Termination UG-20214 | 2019.04.02 Figure 14. SSTL and HSTL I/O Standards External Termination VCCIO_PIO/2 External Termination in Transmitter Pins FPGA On-Board Receiver VCCIO_PIO OCT Termination in Receiver Pins FPGA Transmitter On-Board VCCIO_PIO VCCIO_PIO V REF Series...
  • Page 28 3. Intel Agilex I/O Termination UG-20214 | 2019.04.02 Figure 15. POD12 I/O Standard External Termination VCCIO External Termination in Transmitter Pins FPGA On-Board Receiver CCIO Transmitter OCT Termination in Receiver Pins FPGA On-Board CCIO CCIO Series OCT in Parallel OCT RS...

  • Page 29: Intel Agilex I/O Design Guidelines

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 30: External Memory Interface Pin Placement Requirements

    The following figures show how I/O lanes in various sub-banks are chained together to form the top and bottom I/O rows in Intel Agilex AGF 012 and AGF 014 device variants, respectively. These figures represent the top view of the silicon die that corresponds to a reverse view of the device package.

  • Page 31: Hps Shared I/O Requirements

    The blue line in the above figures shows the connectivity between the sub-banks. For example, in the top row in Intel Agilex AGF 012 and AGF 014 devices: • The top sub-bank in 3A is adjacent to the bottom sub-bank in 3A and the bottom sub-bank in 3B.

  • Page 32: Guidelines For Gpio Pins During Power Sequencing

    I/O standard drive strength settings—ensuring reliability over the lifetime of the devices. 4.10. 1.2 V I/O Interface Voltage Level Compatibility Evaluate the electrical signal level compatibility between Intel Agilex 1.2 V output and the downstream device to ensure the 1.2 V output buffer V and V...
  • Page 33 4. Intel Agilex I/O Design Guidelines UG-20214 | 2019.04.02 • Example 1: — When using 1.2 V LVCMOS, the output signal swings from 0 V to 1.2 V on a lossless transmission line with no external pull-up or pull-down component.

  • Page 34: I/O Simulation

    Output buffer = LOW 4.11. I/O Simulation 4.11.1. HSPICE Models Intel Agilex devices provide a SPICE model which you can use to perform system-level simulations for various configurations. The SPICE kits provide models that support a wide variety of I/O features across process, voltage, and temperature (PVT).

  • Page 35: Intel Agilex High-Speed Serdes I/O Architecture

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 36 Four pairs from the top sub-bank and eight pairs from the bottom sub- bank dedicated SERDES receiver channels support Soft-CDR mode. Refer to the Intel Agilex device pin-out files for the exact location of the Soft-CDR pins. The SERDES transmitter and receiver channels are adjacent to each other. Refer to the Intel Agilex device pin-out files for the exact location of the SERDES pins.
  • Page 37 5. Intel Agilex High-Speed SERDES I/O Architecture UG-20214 | 2019.04.02 Figure 22. SERDES Circuitry This figure shows a transmitter and receiver block diagram for the SERDES circuitry with the interface signals of the transmitter and receiver data paths. The figure shows a transmitter and a receiver sharing an I/O PLL as they are in the same sub-bank and using the same I/O PLL resource.In single data rate (SDR) and double data...

  • Page 38: Intel Agilex Gpio Banks, Serdes, And Dpa Locations

    Figure 23. I/O Bank Structure with I/O PLL, DPA, and SERDES (Bottom View) This figure shows an example of I/O banks in Intel Agilex AGF 012 and AGF 014 devices. The I/O banks availability and locations vary among Intel Agilex devices.

  • Page 39: Intel Agilex Lvds Serdes Transmitter

    5. Intel Agilex High-Speed SERDES I/O Architecture UG-20214 | 2019.04.02 5.2. Intel Agilex LVDS SERDES Transmitter 5.2.1. LVDS SERDES Transmitter Blocks The dedicated circuitry consists of a true differential buffer, a serializer, and I/O PLLs that you can share between the SERDES transmitter and receiver. The serializer takes up to 10 bits wide parallel data from the FPGA fabric.

  • Page 40: Serializer

    5. Intel Agilex High-Speed SERDES I/O Architecture UG-20214 | 2019.04.02 Figure 25. Serializer Bypass This figure shows the serializer bypass path. IOE supports SDR, DDR, or non-registered datapath FPGA Serializer Fabric tx_out tx_in DIN DOUT LVDS SERDES Transmitter tx_coreclock (load_enable, fast_clock, tx_coreclock)

  • Page 41: Differential I/O Bit Position

    5. Intel Agilex High-Speed SERDES I/O Architecture UG-20214 | 2019.04.02 Signal Description (Supported serialization factors: 3–10) Clock for the transmitter fast_clock Enable signal for serialization load_enable LVDS output data stream tx_out 5.2.4. Differential I/O Bit Position Data synchronization is necessary for successful data transmission at high frequencies.

  • Page 42: Clocking Differential Transmitters

    Prime software. The load enable signal is derived from the serialization factor setting. You can configure any Intel Agilex transmitter data channel to generate a source- synchronous transmitter clock output. This flexibility allows the placement of the output clock near the data outputs to simplify board layout and reduce clock-to-data skew.
  • Page 43 5. Intel Agilex High-Speed SERDES I/O Architecture UG-20214 | 2019.04.02 RSDS, and LVPECL compatible signaling. You can statically set the I/O standard of the receiver pins to 1.5 V True Differential Signaling in the Intel Quartus Prime software Assignment Editor or file.
  • Page 44 5. Intel Agilex High-Speed SERDES I/O Architecture UG-20214 | 2019.04.02 5.3.1.1.1. DPA Block The DPA block takes in high-speed serial data from the differential input buffer and selects one of the eight phases that the I/O PLLs generate to sample the data. The DPA chooses a phase closest to the phase of the serial data.
  • Page 45 5. Intel Agilex High-Speed SERDES I/O Architecture UG-20214 | 2019.04.02 5.3.1.1.2. Synchronizer (DPA FIFO) The synchronizer is a one-bit wide and six-bit deep FIFO buffer that compensates for the phase difference between from the DPA block and the dpa_fast_clock that the I/O PLLs produce. The synchronizer can only compensate for fast_clock phase differences, not frequency differences, between the data and the receiver’s...
  • Page 46 5. Intel Agilex High-Speed SERDES I/O Architecture UG-20214 | 2019.04.02 Figure 32. Receiver Data Realignment Rollover This figure shows a preset value of four bit cycles before rollover occurs. The signal pulses rx_bitslip_max for one cycle to indicate that rollover has occurred.

  • Page 47: Clocking Lvds Serdes Receivers

    SGMII protocols. Note: Only the non-DPA mode requires manual skew adjustment. 5.3.3. LVDS SERDES Receiver Modes The Intel Agilex devices support the following receiver modes: • Non-DPA mode • DPA mode •...
  • Page 48 5. Intel Agilex High-Speed SERDES I/O Architecture UG-20214 | 2019.04.02 5.3.3.1. Non-DPA Mode The non-DPA mode disables the DPA and synchronizer blocks. Input serial data is registered at the rising edge of the serial clock that is produced by the fast_clock I/O PLLs.
  • Page 49 SERDES instance can support a maximum of 12 DPA channels. 5.3.3.3. Soft-CDR Mode The Intel Agilex SERDES channel offers the soft-CDR mode to support the GbE and SGMII protocols. A receiver PLL uses the local clock source for reference. Figure 36.

  • Page 50: Intel Agilex Lvds Serdes Source-Synchronous Timing Budget

    In soft-CDR mode, you must place all receiver channels of an SERDES instance in one I/O sub-bank. Top I/O sub-bank can support up to 4 soft-CDR channels and bottom sub-bank can support up to 8 soft-CDR channels.Refer to Intel Agilex device pin-out files to identify the pin locations that support this feature.

  • Page 51: Receiver Skew Margin

    840 Megabits per second (Mbps). The Intel Quartus Prime software Fitter Report panel reports the amount of delay you must add to each trace for the Intel Agilex device. You can use the recommended trace delay numbers shown under the Transmitter/Receiver Package Skew Compensation panel and manually compensate the skew on the PCB board trace to reduce channel-to- channel skew, thus meeting the timing budget between SERDES channels.

  • Page 52: Intel Agilex Lvds Serdes Timing

    RSKM RSKM TCCS TCCS Receiver Input Data This example shows the RSKM calculation for Intel Agilex devices at 1 Gbps data rate with a 200 ps board channel-to-channel skew. • TCCS = 100 ps • SW = 300 ps •...

  • Page 53: I/O Timing Analysis

    Do not use the high-speed clock to drive other logic because the allowed frequency to drive the core logic is restricted by the PLL F specification. For more information about the F specification, refer to the Intel Agilex Device Data Sheet. ® ™...

  • Page 54: Pin Placement For Differential Channels

    DPA usage adds some constraints to the placement of high-speed differential receiver channels. The Intel Quartus Prime compiler automatically checks the design and issues error messages if there are placement guidelines violations. Adhere to the guidelines to ensure proper high-speed I/O operation.

  • Page 55: Documentation Related To The Intel Agilex General Purpose I/O And Lvds Serdes User Guide

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 56: Document Revision History For The Intel Agilex General Purpose I/O And Lvds Serdes User Guide

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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