Intel Stratix 10 Configuration User Manual
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Intel Stratix 10 Configuration User Manual

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  • Page 1 Intel Stratix 10 Configuration User Guide ® ® Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe UG-S10CONFIG | 2018.11.02 Send Feedback Latest document on the web: HTML...

  • Page 2: Table Of Contents

    Stratix 10 Configuration Overview..............4 1.1.1. Configuration and Related Signals..............7 1.1.2. Intel Download Cables Supporting Configuration in Intel Stratix 10 Devices..8 1.2. Intel Stratix 10 Configuration Architecture..............8 1.2.1. Secure Device Manager................9 2. Intel Stratix 10 Configuration Details................12 2.1.
  • Page 3 6.4.1. nCONFIG....................101 6.4.2. nSTATUS....................102 6.4.3. CONF_DONE and INIT_DONE..............102 6.4.4. SDM_IO Pins..................103 7. Intel Stratix 10 Configuration User Guide Archives............. 106 8. Document Revision History for the Intel Stratix 10 Configuration User Guide.....107 Intel Stratix 10 Configuration User Guide Send Feedback...

  • Page 4: Intel ® Stratix ® 10 Configuration Overview

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 5 MSEL security reasons. CvP uses an external PCIe* host device as a Root Port to configure the Intel Stratix 10 device over the PCIe link. You can specify up to a x16 PCIe link. Intel Stratix 10 devices support two CvP modes, CvP init and CvP update.
  • Page 6 In AS fast mode, the SDM first powers the external AS x4 flash. The power supply must be able to provide an equally fast ramp up for the Intel Stratix 10 device and the external AS x4 flash devices. Failing to meet this requirement causes the SDM to assume missing memory.

  • Page 7: Configuration And Related Signals

    This user guide discusses most of the interfaces shown in the figure. Refer to the separate Intel Stratix 10 Configuration via Protocol (CvP) Implementation User Guide and Intel Stratix 10 Power Management User Guide for more information about those features.

  • Page 8: Intel Download Cables Supporting Configuration In Intel Stratix 10 Devices

    1.1.2. Intel Download Cables Supporting Configuration in Intel Stratix 10 Devices Intel provides the following cables to download your design to the Intel Stratix 10 device on the PCB. Download cables support prototyping activity by providing detailed debug messages via Intel Quartus Prime Programmer. You must use Intel download cables for advanced debugging using the Signal Tap logic analyzer the System Console.

  • Page 9: Secure Device Manager

    ® ® 1. Intel Stratix 10 Configuration Overview UG-S10CONFIG | 2018.11.02 Figure 2. Intel Stratix 10 Configuration Architecture Block Diagram Intel Stratix 10 FPGA Secure Device Manager SDM Pins Dual Purpose IO Configurable Network Interface Additional blocks in the Configuration Network...
  • Page 10 You cannot disable this feature. The decompression block in the SDM decompresses both encrypted and non-encrypted configuration files. • A specific PCIe block included in the Intel Stratix 10 device supports CvP. Intel Stratix 10 Configuration User Guide Send Feedback...
  • Page 11 ® ® 1. Intel Stratix 10 Configuration Overview UG-S10CONFIG | 2018.11.02 Related Information SDM Pin Mapping on page 17 Intel Stratix 10 Configuration User Guide Send Feedback...

  • Page 12: Intel Stratix 10 Configuration Details

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 13 Configuration Pass • The SDM enters the Pass state after it completes device configuration. • The Intel Stratix 10 device drives the pin high after CONF_DONE INIT_DONE successful configuration completes. •...

  • Page 14: Intel Stratix 10 Configuration Timing Diagram

    JTAG Configuration Note: You can perform JTAG configuration anytime from any state except the power-on and SDM startup state. The Intel Stratix 10 device cancels the previous configuration and accepts the reconfiguration data from the JTAG interface. The signal must be nCONFIG held in a stable or low state during JTAG configuration.
  • Page 15 MSEL MSEL cycle the Intel Stratix 10 device. Power cycling forces the SDM to sample the MSEL pins before reconfiguring the device. The numbers in the Reconfiguration part of the timing diagram mark the following events: 1.

  • Page 16: Additional Clock Requirements For Transceivers, Hps, Pcie, High Bandwidth Memory (Hbm2) And Smartvid

    2. Intel Stratix 10 Configuration Details UG-S10CONFIG | 2018.11.02 Power Supply Status The power-on reset (POR) holds the Intel Stratix 10 device in the reset state until the power supply outputs are within the recommended operating range. defines the RAMP maximum power supply ramp time.

  • Page 17: Intel Stratix 10 Configuration Pins

    You specify SDM I/O pin functions using the Device Configuration Device and Pin Options dialog box in the Intel Quartus Prime software. Refer to the Intel Stratix 10 Device Pinouts and Intel Stratix 10 Pin Connection Guidelines for more details on other functions. Table 3.

  • Page 18: Msel Settings

    DIRECT_TO_FAC TORY SEU_ERROR Related Information Intel Stratix 10 Device Pinouts 2.4.2. MSEL Settings pins set the configuration scheme for Intel Stratix 10 devices. Use MSEL[2:0] 4.7-kΩ resistors to pull the pins up to V or down to ground as MSEL[2:0]...

  • Page 19: Device Configuration Pins

    18 ms. This ramp-up requirement ensures that the AS x4 device VCCIO_SDM is within its operating voltage range when the Intel Stratix 10 device begins to access it. JTAG configuration works with any MSEL settings, unless disabled for security.
  • Page 20 Bidirectional SDMMC_CFG_DATA[7:0] CCIO_SDM SD/MMC Output SDMMC_CFG_CCLK CCIO_SDM 2.4.3.1. Configuration Pins I/O Standard and Drive Strength Table 6. Intel Stratix 10 Configuration Pins I/O Standard and Drive Strength Configuration Pin Direction I/O Standard Drive Strength (mA) Function Output 1.8V LVCMOS Input Schmitt Trigger Input —...

  • Page 21: Setting Additional Configuration Pins

    SDM_IO[16:0] All other configuration Schmitt Trigger Input or 1.8V LVCMOS pins Unused SDM Pins You can specify other functions on unused SDM pins in the Intel Quartus Prime software. Table 7. Additional Configuration Pins Note: To avoid false signaling indicating successful configuration, Intel recommends that you include an external weak pull-down resistor for pins.

  • Page 22: Enabling Dual-Purpose Pins

    2. Intel Stratix 10 Configuration Details UG-S10CONFIG | 2018.11.02 4. Click OK to confirm and close the Configuration Pin dialog box. 2.4.5. Enabling Dual-Purpose Pins , and are dual- AVST_CLK AVST_DATA[15:0] AVST_DATA[31:16] AVST_VALID purpose pins. Once the device enters user mode these pins can function either as GPIOs or as tri-state inputs.

  • Page 23: Setting Configuration Clock Source

    2. Intel Stratix 10 Configuration Details UG-S10CONFIG | 2018.11.02 4. Click OK to confirm and close the Device and Pin Options. 2.5. Setting Configuration Clock Source You must specify the configuration clock source by selecting either the internal oscillator or with the supported frequency.

  • Page 24: Configuration Clocks

    OSC_CLK_1 between 170-230 MHz. Intel Stratix 10 devices always use this internal oscillator to load the first section of the bitstream (approximately 200 kilobyte (KB). The SDM can use either clock source for the remainder of device configuration. If you use the internal oscillator, can you leave the unconnected.

  • Page 25: Configuration And Programming Files

    2. Intel Stratix 10 Configuration Details UG-S10CONFIG | 2018.11.02 2.7. Configuration and Programming Files Intel Stratix 10 configuration and external flash programming involves multiple file types and tools. Figure 6. Overview of Intel Quartus Prime Supported Files and Tools for Configuration...
  • Page 26 Serial Vector Format ( /SVF) .svf Related Information • Can I use 3rd party QSPI flash devices for Active Serial configuration of Intel Stratix 10 devices? • Using the Command-Line Jam STAPL Solution for Device Programming • Intel FPGA IP for Configuration - Support Center...

  • Page 27: Intel Stratix 10 Configuration Schemes

    You can use the PFL II IP core with a MAX II, MAX V, or Intel MAX 10 device as the host to read configuration data from the flash memory device and configure the Intel Stratix 10 device.

  • Page 28: Enabling Avalon-St Device Configuration

    AVST_data[31:0]] The configuration files for Intel Stratix 10 devices can be highly compressed. During configuration, the decompression of the bit stream inside the device requires the host to pause before sending more data. The Intel Stratix 10 device asserts the signal when the device is ready to accept data.
  • Page 29 FPGA or to indicate the configuration process is complete. If you use the PFL II IP core as the configuration host, you can use the Intel Quartus Prime software to store the binary configuration data to the flash memory through the PFL II IP core.

  • Page 30: Avalon-St Single-Device Configuration

    3. Intel Stratix 10 Configuration Schemes UG-S10CONFIG | 2018.11.02 3.1.3. Avalon-ST Single-Device Configuration Refer to the Intel Stratix 10 Device Family Pin Connection Guidelines for additional information about individual pin usage and requirements. Figure 8. Connections for Avalon-ST x8 Single-Device Configuration...
  • Page 31 3. Intel Stratix 10 Configuration Schemes UG-S10CONFIG | 2018.11.02 Figure 9. Connections for Avalon-ST x16 Single-Device Configuration CCIO_SDM External Host Configuration Control Signals Intel® Stratix®10 CPLD / FPGA 10kΩ fpga_nconfig nCONFIG nSTATUS fpga_nstatus fpga_conf_done CONF_DONE INIT_DONE Parallel Flash Loader II IP...

  • Page 32: Rbf Configuration File Format

    18 • Intel Stratix 10 Device Family Pin Connection Guidelines 3.1.4. RBF Configuration File Format If you do not use the Parallel Flash Loader II Intel FPGA IP core to program the flash, you must generate the file. .rbf...

  • Page 33: Debugging Guidelines For The Avalon-St Configuration Scheme

    • If using x16 or x32 mode, power the IO bank containing the x16 or x32 pins (3A) at 1.8V. • Ensure you select the appropriate Avalon-ST configuration scheme in your Intel Quartus Prime Pro Edition project. • Ensure the pins reflect this mode.

  • Page 34: Ip For Use With The Avalon-St Configuration Scheme: Intel Fpga Parallel Flash Loader Ii Ip Core

    You can either program the CPLD and the flash memory concurrently or separately. You can use the Parallel Flash Loader II Intel FPGA IP core (PFL II) with an external host, such as the MAX II, MAX V, or Intel MAX 10 devices to complete the following tasks: •...
  • Page 35 3.1.6.1.2. Controlling Avalon-ST Configuration with PFL II IP Core The PFL II IP core in the host determines when to start the configuration process, read the data from the flash memory device, and configure the Intel Stratix 10 using the Avalon-ST configuration scheme.
  • Page 36 You have JTAG or In-System Programming (ISP) access to the configuration host. • You want to program the flash memory device with non-Intel FPGA data. For example, the flash memory device contains initialization storage for an ASSP. You can use the PFL II IP core to program the flash memory device for the following purposes: —...
  • Page 37 0×2000 • Auto mode—allows the Intel Quartus Prime software to automatically determine the start address of the page. The Intel Quartus Prime software aligns the pages on a 128-KB boundary; for example, if the first valid start address is 0×000000 the next valid start address is an increment of 0×20000...
  • Page 38 0x40 0x7F (11) .pof version 0x80 Reserved 0x81 0xFF The Intel Quartus Prime Convert Programming File tool generates the information for version when you convert the files to files. .pof .sof .pof The value for the version for Intel Stratix 10 is .pof...
  • Page 39 3. Intel Stratix 10 Configuration Schemes UG-S10CONFIG | 2018.11.02 3.1.6.1.6. Restoring Option Bit Start and End Address You can restore the start and end address that you specified for each of the SOF page when converting a file from the 32-bit value of the sector offset .sof...
  • Page 40 3. Intel Stratix 10 Configuration Schemes UG-S10CONFIG | 2018.11.02 0000000000011100000000000000000000 0x700000 Page 1 end address = appends with 0x00352E30 2’b11 0000000000110101001011100011000011 0xD4B8C3 The start and end address must be correlated with the start and end address for each page printed in the file.
  • Page 41 3. Intel Stratix 10 Configuration Schemes UG-S10CONFIG | 2018.11.02 FPGA Configuration Option bits Figure 19. Page Start Address, End Address, and Page-Valid Bit Stored as Option Bits Bits 0 to 12 for the page start address are set to zero and are not stored as option bits. The Page-Valid bits indicate whether each page is successfully programmed.
  • Page 42 7. Select SOF Data and click Properties to set the page number and name. Under Address scheme for selected pages, select Auto to let the Intel Quartus Prime software automatically set the start address for that page. Select Block to specify the start and end addresses or select Start to specify the start address only and click OK.
  • Page 43 3. Intel Stratix 10 Configuration Schemes UG-S10CONFIG | 2018.11.02 • If you select absolute addressing mode, the data in the .hex programmed in the flash memory device at the same address location listed in the .hex • If you select relative addressing mode, specify a start address. The data in is programmed into the flash memory device with the specific...
  • Page 44 3. Intel Stratix 10 Configuration Schemes UG-S10CONFIG | 2018.11.02 3.1.6.2.2. Creating Separate PFL II Functions 1. To create a PFL II instantiation, select Flash Programming Only mode. 2. Assign the pins appropriately. 3. Compile and generate a for the flash memory device. Ensure that you tri- .pof...
  • Page 45 Description Add new Intel- or AMD-compatible CFI flash memory device into the PFL II-supported flash database. Edit Edit the parameters of the newly added Intel- or AMD-compatible CFI flash memory device in the PFL II-supported flash database. Remove Remove the newly added Intel- or AMD-compatible CFI flash memory device from the PFL II- supported flash database.
  • Page 46 Specify the CFI flash extended device identifier, only applicable for AMD- compatible CFI flash memory device Flash device is Intel compatible Turn on the option if the CFI flash is Intel compatible Typical word programming time Typical word programming time value in µs unit Maximum word programming time Maximum word programming time value in µs unit...
  • Page 47 Specifies the access time of the flash. You can get the time maximum access time that a flash memory device requires from the flash datasheet. Intel recommends specifying a flash access time that is the same as or longer than the required time.
  • Page 48 For more information about the read-access modes of the flash memory device, refer to the respective flash memory data sheet. Latency count • Specify the latency count for Intel Burst Read mode. Only available when you enable Intel Burst Mode. • • Intel Stratix 10 Configuration User Guide...
  • Page 49 3. Intel Stratix 10 Configuration Schemes UG-S10CONFIG | 2018.11.02 3.1.6.4. Signals Table 22. PFL II Signals Type Weak Pull- Function Input — Asynchronous reset for the PFL II IP core. Pull high pfl_nreset to enable FPGA configuration. To prevent FPGA configuration, pull low when you do not use the PFL II IP core.
  • Page 50 A low signal resets the flash memory device. continued... (12) Intel recommends not inserting logic between the PFL II pins and the host I/O pins, especially on the flash_data and fpga_nconfig pins. Intel Stratix 10 Configuration User Guide Send Feedback...

  • Page 51: As Configuration

    Avalon Interface Specifications 3.2. AS Configuration In AS configuration schemes, the SDM block in the Intel Stratix 10 device controls the configuration process and interfaces. The serial flash configuration devices store the configuration data. During AS Configuration, the SDM first powers on with boot ROM.

  • Page 52: As Using Multiple Serial Flash Devices

    Intel Stratix 10 Device Family Pin Connection Guidelines 3.2.2. AS Using Multiple Serial Flash Devices Intel Stratix 10 devices support one AS x4 flash memory device for AS configuration and up to three AS x4 flash memories for use with HPS data storage. The...

  • Page 53: As Configuration Timing

    , when the device powers on. AS_DATA3 AS_CS0 AS_CS3 Note: When using multiple flash devices, the clock frequency must be reduced. Refer to the Intel Stratix 10 Device Datasheet for more information. Related Information • MSEL Settings on page 18 •...

  • Page 54: Programming Serial Flash Devices

    AS_CLK ext_delay AS_DATA Note: For more information about the timing parameters, refer to the Intel Stratix 10 Device Datasheet. 3.2.4. Programming Serial Flash Devices You can program serial flash devices in-system using the Intel FPGA Download Cable II or Intel FPGA Ethernet Cable.
  • Page 55 JTAG. When is set to JTAG, the SDM tristates the AS pins allowing MSEL MSEL the Intel Quartus Prime Programmer to program the flash memory devices via the AS header. Figure 25. AS Programming Using Intel Quartus Prime or Third-Party Programmer CCIO_SDM 10 kΩ...

  • Page 56: Serial Flash Memory Layout

    SDM drives configuration data from the programmer to the AS x4 flash device using SDM_IOs. 4. To use the Intel Stratix 10 device in AS mode after successful programming of the flash device, set the MSEL pins to either AS fast or AS normal mode and power cycle the device.

  • Page 57: As_Clk

    , ensure that the .rpd configuration data is stored starting from address 0 of the serial flash device. If you files, the Intel Stratix 10 Programmer automatically programs the .jic .pof configuration data starting from address 0 of the serial flash device.

  • Page 58: Active Serial Configuration Software Settings

    • 3.2.7. Active Serial Configuration Software Settings You must set the parameters in the Device and Pin Options of the Intel Quartus Prime software when using the AS configuration scheme. To set the parameters for AS configuration scheme, complete the following steps: 1.

  • Page 59: Generating And Programming As Configuration Programming Files

    3. Intel Stratix 10 Configuration Schemes UG-S10CONFIG | 2018.11.02 3.2.8. Generating and Programming AS Configuration Programming Files You must perform the following steps before configuring the Intel Stratix 10 using AS configuration scheme: 1. Generate , or programming files using Convert Programming .pof...
  • Page 60 3. Intel Stratix 10 Configuration Schemes UG-S10CONFIG | 2018.11.02 5. In the File name field, specify the file name for the programming file you want to create. 6. Under Advanced to generate a Memory Map File ( ), turn on Create .map...

  • Page 61: Debugging Guidelines For The As Configuration Scheme

    AS fast or MSEL MSEL normal, the SDM drives the AS pins until you power cycle the Intel Stratix 10 device. Unlike earlier device families, the AS pins are not tristated when the device enters user mode. The AS configuration scheme has power-on requirements. If you use AS Fast mode...

  • Page 62: Configuration From Sd Mmc

    18 ms. CCIO_SDM • Ensure that the flash is powered up and ready to be accessed when the Intel Stratix 10 device exists power-on reset. • If you are using an external clock source for configuration, ensure the...

  • Page 63: Jtag Configuration

    JTAG-chain device programming is ideal during development. You can reconfigure Intel Stratix 10 using JTAG faster than you can reprogram flash memory. You can also use JTAG to reprogram a corrupted flash memory that is preventing the Intel Stratix 10 device from configuring using its normal configuration scheme.

  • Page 64: Jtag Single-Device Configuration

    The configuration data is available on the pin one clock cycle later. You can configure the Intel Stratix 10 device through JTAG using a download cable or a microprocessor. 3.4.1.1. JTAG Single-Device Configuration using Download Cable Connections Refer to the Intel Stratix 10 Device Family Pin Connection Guidelines for additional information about individual pin usage and requirements.
  • Page 65 Intel Stratix 10 Device Family Pin Connection Guidelines 3.4.1.2. JTAG Single-Device Configuration using a Microprocessor Refer to the Intel Stratix 10 Device Family Pin Connection Guidelines for additional information about individual pin usage and requirements. Intel Stratix 10 Configuration User Guide...

  • Page 66: Jtag Multi-Device Configuration

    If you have four or more devices in a JTAG chain, buffer the , and pins with an on-board buffer. You can also connect other Intel FPGA devices with JTAG support to the chain. Intel Stratix 10 Configuration User Guide...

  • Page 67: Debugging Guidelines For The Jtag Configuration Scheme

    Intel Quartus Prime Programmer to detect the device. If the programmer can detect the Intel Stratix 10 device, it has exited the POR state. • If using an Intel FPGA Download Cable II, reduce the cable clock speed to 6 MHz. Intel Stratix 10 Configuration User Guide Send Feedback...
  • Page 68 UG-S10CONFIG | 2018.11.02 • If you have multiple devices in the JTAG chain, try to disconnect other devices from the JTAG chain to isolate the Intel Stratix 10 device. • If you specify the as the clock source for configuration, ensure that...

  • Page 69: Stratix 10 Configuration Features

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 70 4. Stratix 10 Configuration Features UG-S10CONFIG | 2018.11.02 Figure 35. Intel Stratix 10 CvP Configuration Block Diagram Intel® Stratix®10 CVP_CONFDONE (optional) CCIO_SDM Configuration 10kΩ Control Signals nCONFIG nSTATUS Optional CONF_DONE Monitoring INIT_DONE OSC_CLK_1 MSEL MSEL[2:0] Configuration Control Signals FPGA Fabric...

  • Page 71: Partial Reconfiguration

    You can perform CvP update on a device that you originally configure using CvP initialization or any other configuration scheme. Related Information Intel Stratix 10 Configuration via Protocol (CvP) Implementation User Guide 4.3. Partial Reconfiguration Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function.

  • Page 72: Remote System Upgrade

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 73 Stratix 10 Data Remote Connection Flash Development Data Memory Location Data System Board Remote Connection Stratix 10 Active FPGA Configuration Flash Memory RSU Setup Related Information Altera Remote Update IP Core User Guide Intel Stratix 10 Configuration User Guide Send Feedback...

  • Page 74: Remote System Upgrade Functional Description

    Designs that do not use the HPS as the remote system upgrade host require an Intel Stratix 10 Serial Flash Mailbox Client FPGA IP core as shown in the figure below. The Serial Mailbox Client sends and receives remote system upgrade operation commands and responses.

  • Page 75: Remote System Upgrade Configuration Images

    The application image can be added or obtained after you configure the device with the factory image. Depending on the storage space of your flash memory, Intel Stratix 10 remote system upgrade supports one factory application image and up to 507 application images. The Quartus Programming File Generator only supports up to three remote system upgrade images.

  • Page 76: Remote System Upgrade Configuration Sequence

    SDM pin. The SDM loads the application image if you do not assign this pin. 3. The configuration firmware pointer block in the flash device maintains a list of pointers to the application images. Intel Stratix 10 Configuration User Guide Send Feedback...

  • Page 77: Guidelines For Performing Remote System Upgrade Functions For Non-Hps

    (SDM) Master Bridge) Note: Refer to the Intel Stratix 10 SoC Development Kit User Guide for more details on using HPS as the RSU host to perform remote system upgrade. Here are guidelines to follow when implementing remote system upgrade: 1.

  • Page 78: Commands And Error Codes

    29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED LENGTH COMMAND / ERROR CODE The following table describes the fields of the header command. Table 27. Mailbox Client Intel Stratix 10 FPGA IP Command and Error Code Header Description Header Description Reserved [31:28] Reserved.

  • Page 79: Operation Commands

    5. Remote System Upgrade UG-S10CONFIG | 2018.11.02 5.3.1. Operation Commands Table 28. Mailbox Client Intel Stratix 10FPGA IP Command List and Description Command Code Number Number Description (Hex) Command Response (13) (13) Triggers reconfiguration from data source or configuration data stored in RSU_IMAGE_ AS x4 flash memory.
  • Page 80 Returns 0 for no error. Clients use this command to request exclusive access AS x4 interface. QSPI_OPEN The SDM returns the appropriate response: continued... (13) The number does not include the command and response header. Intel Stratix 10 Configuration User Guide Send Feedback...
  • Page 81 The number of bytes to write. The maximum size is 8 bytes. • The data. The maximum write is 2 words, padded with 0 to the word boundary. continued... (13) The number does not include the command and response header. Intel Stratix 10 Configuration User Guide Send Feedback...

  • Page 82: Error Code Responses

    DEVICE_OP A successful command returns an OK response code. 5.3.2. Error Code Responses Table 29. Mailbox Client Intel Stratix 10 FPGA IP Error Code Responses and Description Value (Hex) Error Code Response Description Indicates that the command completed successfully. .

  • Page 83: Remote System Upgrade Flash Device Layout

    5. Remote System Upgrade UG-S10CONFIG | 2018.11.02 5.4. Remote System Upgrade Flash Device Layout The Intel Quartus Prime Programming Files Generator populates the flash memory when you generate the remote system upgrade programming files. Table 30. Remote System Upgrade Flash Memory Layout The start of flash address 0, or the A2 partition within a partitioned flash address 0, must be set up as shown in the following table.

  • Page 84: Generating Remote System Upgrade Image Files Using Programming File Generator

    Reserved 5.5. Generating Remote System Upgrade Image Files using Programming File Generator Use the Intel Quartus Prime Programming File Generator tool to generate the Intel Stratix 10 remote system upgrade flash programming files. 5.5.1. Generating a Standard RSU Image Follow these steps to generate a standard RSU image: 1.

  • Page 85: Generating A Single Rsu Image

    .sof file drop-down list and click OK. Note: You must assign Page 0 to Factory Image. Intel recommends that you let the Intel Quartus Prime software assign the Start address of the automatically by retaining the default value for Address FACTORY_IMAGE Mode which is Auto.

  • Page 86: Remote System Upgrade From Fpga Core Example

    3. Reconfiguring the device with an application or factory image. 4. Creating a single remote system update ( ) containing the bitstreams to add .rpd an application image in user mode. 5. Adding an application image. 6. Removing an application image. Intel Stratix 10 Configuration User Guide Send Feedback...

  • Page 87: Prerequisites

    You should be running the Intel Quartus Prime Pro Edition software version 18.0 Update 1 or later. • You should create and download this example to the Intel Stratix 10 SoC Development Kit. • Your design should include the Mailbox Client Intel Stratix 10 FPGA IP that connects to a JTAG to Avalon Master Bridge as shown the Platform Designer system.
  • Page 88 7. In the Configuration Device tab, click Add Device, select MT25QU02G flash memory and click OK. The Programming File Generator tool automatically populates the flash partitions. 8. Select the FACTORY_IMAGE partition and click Edit. Intel Stratix 10 Configuration User Guide Send Feedback...
  • Page 89 .sof settings for Address Mode. Click OK. 12. For Flash loader click Select. Select Stratix 10 from Device family list. Select 1SX280LU3S2 for the Device name. Click OK. 13. Click Generate to generate the remote system upgrade programming files. The two following files are generated: Initial_RSU_Image.jic...
  • Page 90 UG-S10CONFIG | 2018.11.02 Notes: - Data checksum for this conversion is 0xBFFB90A5 - All the addresses in this file are byte addresses After generating the programming file, you can program the flash memory. Intel Stratix 10 Configuration User Guide Send Feedback...

  • Page 91: Programming Flash Memory With Initial Remote System Upgrade Image

    Start. 4. Configuration is complete when the progress bar reaches 100%. Power cycle the board to automatically configure the Intel Stratix 10 device with the application image using the AS x4 configuration scheme. Note: This example does not assign the direct to factory pin. Consequently, the programmer configures the device with the application image.

  • Page 92: Reconfiguring The Device With An Application Or Factory Image

    5. Remote System Upgrade UG-S10CONFIG | 2018.11.02 a. In the Intel Quartus Prime software, select Tools System Debugging Tools System Console to launch the system console. b. In the Tcl Console pane, type to open the example of Tcl source rsu1.tcl script to perform the remote system upgrade commands.

  • Page 93: Adding An Application Image

    QSPI_WRITE 2. Alternatively, the script includes the function that rsu1.tcl program_flash programs a new application image into flash memory. The following command accomplishes this task: program_flash new_application_image.rpd 0x03FF0000 1024 Intel Stratix 10 Configuration User Guide Send Feedback...
  • Page 94 You can use the function verify that the new image pointer slot value is qspi_read . The function takes in two arguments: 0xFFFFFFFF qspi_read 1. Start address 2. Number of words to read Intel Stratix 10 Configuration User Guide Send Feedback...
  • Page 95 Verifying the Update to the New Image Pointer Slot at 0x00234028 Host software can now reconfigure the Intel Stratix 10 FPGA with the new application image by asserting the pin.

  • Page 96: Removing Application Image

    CPB0 + 0x28 0x002E4028 0x03FF0000 pointer slot (highest priority) CPB1 + Old application image pointer slot 0x20 0x002EC020 0x002F4000 (lower priority) Current/New application image CPB1 + 0x28 0x002EC028 0x03FF0000 pointer slot (highest priority) Intel Stratix 10 Configuration User Guide Send Feedback...
  • Page 97 You can run the report to check the status nCONFIG rsu_status of the current image address, 0x002f4000 Intel Stratix 10 Configuration User Guide Send Feedback...

  • Page 98: Intel Stratix 10 Debugging Guide

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 99 SDM_IO9 MSEL[2] MSEL configuration mode selected. Do not connect directly to power. Use 4.7 KΩ pull-up or pull-downs, as appropriate. No longer Open Drain. Intel recommends a 10 KΩ pull-up to NSTATUS nSTATUS CCIO_SDM Not Available Multi-device configuration is not supported.

  • Page 100: Configuration File Format Differences

    .sof Programmer adds the firmware to the to the . The programmer adds the .sof firmware when configuring an Intel Stratix 10 device or when it converts the .sof another format. 6.4. Understanding and Troubleshooting Configuration Pin Behavior Configuration typically fails for one of the following reasons: •...

  • Page 101: Nconfig

    OSC_CLK_1 Intel Quartus Prime. • Try configuring the Intel Stratix 10 device with a simple design that does not contain any IP. If configuration via a non-JTAG scheme fails with a simple design, try JTAG configuration with the pins set specifically to JTAG.

  • Page 102: Nstatus

    INIT_DONE , weak internal pull-downs pull these pins low at power-on SDM_IO16 SDM_IO0 reset. Ensure you specify these pins in the Intel Quartus Prime Software or in the Intel Quartus Prime settings file, ( are low prior to and .qsf...

  • Page 103: Sdm_Io Pins

    SDM_IO weakly high during power-on. Debugging Suggestions Check the Intel Quartus Prime Pro Edition settings and Fitter report to ensure that the configuration matches your PCB design. The following screen shots show SDM_IO where to configure these signals and how to confirm the...
  • Page 104 6. Intel Stratix 10 Debugging Guide UG-S10CONFIG | 2018.11.02 Figure 46. Configuration Pin Selection in the Intel Quartus Prime Pro Edition Software Intel Stratix 10 Configuration User Guide Send Feedback...
  • Page 105 6. Intel Stratix 10 Debugging Guide UG-S10CONFIG | 2018.11.02 Figure 47. Fitter Report and SDM_IO Pin Reporting Starting with the Intel Quartus Prime Pro Edition Software, version 18.1, an SDM debug tool is available through the System Console, Tools System Debugging Tools System Console Stratix 10 SDM Debug.

  • Page 106: Intel Stratix 10 Configuration User Guide Archives

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 107: Document Revision History For The Intel Stratix 10 Configuration User Guide

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 108 8. Document Revision History for the Intel Stratix 10 Configuration User Guide UG-S10CONFIG | 2018.11.02 Document Version Intel Quartus Changes Prime Version • Moved almost all of the material describing the PFL II flash from an appendix to the Intel Stratix 10 Configuration Schemes chapter.
  • Page 109 8. Document Revision History for the Intel Stratix 10 Configuration User Guide UG-S10CONFIG | 2018.11.02 Date Version Changes • Added Configuration Pins I/O Standard and Drive Strength table. • Updated information about maximum additional data words when using 2-stage register synchronizer.
  • Page 110 8. Document Revision History for the Intel Stratix 10 Configuration User Guide UG-S10CONFIG | 2018.11.02 Date Version Changes • Added note to Avalon-ST in Stratix 10 Configuration Overview table. • Updated ASx4 max data rate in Stratix 10 Configuration Overview table.
  • Page 111 Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 112 The PFL II IP core supports top and bottom boot block of the flash memory devices. For Micron flash memory devices, the PFL II IP core supports top, bottom, and symmetrical blocks of flash memory devices. Intel Stratix 10 Configuration User Guide Send Feedback...
  • Page 113 The PFL II IP core supports top and bottom boot block of the flash memory devices. For Micron flash memory devices, the PFL II IP core supports top, bottom, and symmetrical blocks of flash memory devices. (17) Intel tested flash device. (18) Supports page mode. Intel Stratix 10 Configuration User Guide Send Feedback...

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