Specifying The Pts Count - Intel 8XC196K Series User Manual

Table of Contents

Each PTS control block (PTSCB) requires eight data bytes in register RAM. The address of the

first (lowest) byte is stored in the PTS vector table in special-purpose memory (see "Special-pur-

pose Memory" on page 4-3). Figure 5-9 shows the PTSCB for each PTS mode. Unused PTSCB

bytes can be used as extra RAM.

The PTSCB must be located in register RAM. The location of the first byte of

the PTSCB must be aligned on a quad-word boundary (an address evenly

divisible by 8).

Specifying the PTS Count

For single transfer, block transfer, and A/D scan routines, the first location of the PTSCB contains

an 8-bit value called PTSCOUNT. This value defines the number of interrupts that will be ser-

viced by the PTS routine. The PTS decrements PTSCOUNT after each PTS cycle. When

PTSCOUNT reaches zero, hardware clears the corresponding PTSSEL bit and sets the PTSSRV

bit (Figure 5-10), which requests an end-of-PTS interrupt. The end-of-PTS interrupt service rou-

tine should reinitialize the PTSCB, if required, and set the appropriate PTSSEL bit to re-enable

PTS interrupt service.

Figure 5-9. PTS Control Blocks

STANDARD AND PTS INTERRUPTS

PTSCONST2 (H)

PTSCONST2 (L)

PTSCONST1 (H)

PTSCONST1 (L)

PTSCONST1 (H)

PTSCONST1 (L)