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8XC196K x , J x , CA USER'S MANUAL
Table 15-1. External Memory Interface Signals (Continued)
Function
Type
Name
ALE
O
Address Latch Enable
This active-high output signal is asserted only during external
memory cycles. ALE signals the start of an external bus cycle and
indicates that valid address information is available on the system
address/data bus. ALE differs from ADV# in that it does not remain
active during the entire bus cycle.
An external latch can use this signal to demultiplex the address from
the address/data bus.
†
BHE#
O
Byte High Enable
The chip configuration register 0 (CCR0) determines whether this pin
functions as BHE# or WRH#. CCR0.2=1 selects BHE#; CCR0.2=0
selects WRH#.
During 16-bit bus cycles, this active-low output signal is asserted for
word reads and writes and high-byte reads and writes to external
memory. BHE# indicates that valid data is being transferred over the
upper half of the system data bus. BHE#, in conjunction with AD0,
indicates the memory byte that is being transferred over the system
bus:
BHE#
0
0
1
†
†
BREQ#
O
Bus Request
This active-low output signal is asserted during a hold cycle when
the bus controller has a pending external memory cycle.
The device can assert BREQ# at the same time as or after it asserts
HLDA#. Once it is asserted, BREQ# remains asserted until HOLD#
is removed.
You must enable the bus-hold protocol before using this signal (see
"Enabling the Bus-hold Protocol (8XC196Kx Only)" on page 15-18).
†
†
BUSWIDTH
I
Bus Width
The chip configuration register bits, CCR0.1 and CCR1.2, along with
the BUSWIDTH pin, control the data bus width. When both CCR bits
are set, the BUSWIDTH signal selects the external data bus width.
When only one CCR bit is set, the bus width is fixed at either 16 or 8
bits, and the BUSWIDTH signal has no effect.
CCR0.1 CCR1.2 BUSWIDTH
0
1
1
1
†
15-2
AD0 Byte(s) Accessed
0
both bytes
1
high byte only
0
low byte only
This pin is not implemented on the 8XC196J x device.
This pin is not implemented on the 87C196CA, 8XC196J x devices.
1
N/A
0
N/A
1
high
1
low
This pin is not implemented on the 87C196CA, 8XC196J x devices.
Description
fixed 8-bit data bus
fixed 16-bit data bus
16-bit data bus
8-bit data bus
Multiplexed
With
ADV#/P5.0
P5.5/WRH#
P2.3
P5.7
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