Table of Contents
Advertisement
I/O PORTS
6.4.3
Design Considerations for Ports 3 and 4
When EA# is active, ports 3 and 4 will function only as the address/data bus. In these circum-
stances, an instruction that operates on P3_REG or P4_REG causes a bus cycle that reads from
or writes to the external memory location corresponding to the SFR's address. (For example, writ-
ing to P4_REG causes a bus cycle that writes to external memory location 1FFDH.) Because
P3_REG and P4_REG have no effect when EA# is active, the bus will float during long periods
of inactivity (such as during a BMOV or TIJMP instruction).
When EA# is inactive, ports 3 and 4 output the contents of the P3_REG and P4_REG registers.
Because these registers reset to FFH and the P34_DRV register resets to 00H (open-drain mode),
ports 3 and 4 will float unless you either connect external resistors to the pins, write zeros to the
P3_REG and P4_REG registers, or write ones to the P34_DRV register.
6-19
Advertisement
Table of Contents
