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Table A-9. Instruction Execution Times (in State Times) (Continued)
Mnemonic
DIV
DIVB
DIVU
DIVUB
MUL (2 ops)
MUL (3 ops)
MULB (2 ops)
MULB (3 ops)
MULU (2 ops)
MULU (3 ops)
MULUB (2 ops)
MULUB (3 ops)
Mnemonic
AND (2 ops)
AND (3 ops)
ANDB (2 ops)
ANDB (3 ops)
NEG
NEGB
NOT
NOTB
OR
ORB
XOR
XORB
NOTE: The column entitled "Reg." lists the instruction execution times for accesses to the register file or
peripheral SFRs. The column entitled "Mem." lists the instruction execution times for accesses to
all memory-mapped registers, I/O, or memory. See Table 4-1 on page 4-2 for address information.
Arithmetic (Group II)
Direct
Immed.
Normal
Reg.
26
27
28
18
18
20
24
25
26
16
16
18
16
17
18
16
17
18
12
12
14
12
12
14
14
15
16
14
15
16
10
10
12
10
10
12
Logical
Direct
Immed.
Normal
Reg.
4
5
6
5
6
7
4
4
6
5
5
7
3
—
3
—
3
—
3
—
4
5
6
4
4
6
4
5
6
4
4
6
INSTRUCTION SET REFERENCE
Indirect
Autoinc.
Mem.
Reg.
Mem.
31
29
32
23
21
24
29
27
30
21
19
22
21
19
22
21
19
22
17
15
18
17
15
18
19
17
19
19
17
19
15
13
15
15
13
15
Indirect
Autoinc.
Mem.
Reg.
Mem.
8
7
9
10
8
11
8
7
9
10
8
11
—
—
—
—
—
—
—
—
8
7
9
8
7
9
8
7
9
8
7
9
Indexed
Short
Long
Reg.
Mem.
Reg.
Mem.
29
32
30
33
21
24
22
25
27
30
28
31
19
22
20
23
19
22
20
23
19
22
20
23
15
18
16
19
15
18
16
19
17
20
18
21
17
20
18
21
12
16
14
17
12
16
14
17
Indexed
Short
Long
Reg.
Mem.
Reg.
Mem.
6
8
7
7
10
8
11
6
8
7
7
10
8
11
—
—
—
—
—
—
—
—
6
8
7
6
8
7
6
8
7
6
8
7
A-55
9
9
9
9
9
9
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