Programmable Bus Hold; Programmable Pull-Up Resistor; Programmable Pre-Emphasis - Intel Agilex User Manual

You can attach several open-drain outputs to a wire. This connection type is like a
logical OR function, and is commonly called an active-low wired-OR circuit. If at least
one of the outputs is in logic 0 state (active), the circuit sinks the current and brings
the line to low voltage.
You can use open-drain output if you are connecting multiple devices to a bus. For
example, you can use the open-drain output for system-level control signals that can
be asserted by any device or as an interrupt.
Do not pull the output voltage higher than the
you perform HSPICE simulation to verify the output voltage in your selected topology.
Ensure the output voltage meets the VIH and VIL requirements of the receiving
device.

2.2.4. Programmable Bus Hold

Intel Agilex devices support the programmable bus hold feature on 1.2 V LVCMOS
output. Each I/O pin provides an optional bus-hold feature that is active only after
configuration. When the device enters user mode, the bus-hold circuit captures the
value that is present on the pin by the end of the configuration.
The bus-hold circuitry uses a resistor to weakly pull the signal level to the last-driven
state of the pin. The bus-hold circuitry holds this pin state until the next input signal is
present. Therefore, you do not require an external pull-up or pull-down resistor to
hold a signal level when the bus is tri-stated.
For each I/O pin, you can individually specify that the bus-hold circuitry pulls non-
driven pins away from the input threshold voltage—where noise can cause unintended
high-frequency switching. To prevent over-driving signals, the bus-hold circuitry drives
the voltage level of the I/O pin lower than the
If you enable the bus-hold feature, you cannot use the programmable pull-up option.

2.2.5. Programmable Pull-Up Resistor

Intel Agilex devices support programmable pull up resistor on 1.2 V LVCMOS I/O. Each
I/O pin provides an optional programmable pull-up resistor during user mode.
The programmable pull-up resistor feature is enabled by default on unused I/O for
both 1.2 V and 1.5 V
VCCIO_PIO
If you enable the weak pull-up resistor, you cannot use the bus-hold feature.

2.2.6. Programmable Pre-Emphasis

The V
OD
a high-speed transmission signal. At a high frequency, the slew rate may not be fast
enough to reach the full V
jitter. With pre-emphasis, the output current is boosted momentarily during switching
to increase the output slew rate.
Pre-emphasis increases the amplitude of the high-frequency component of the output
signal, and thus helps to compensate for the frequency-dependent attenuation along
the transmission line. The overshoot introduced by the extra current happens only
during a change of state switching to increase the output slew rate, and does not ring,
® ™
Intel Agilex General Purpose I/O and LVDS SERDES User Guide
16
VCCIO_PIO
level.
setting and the output impedance of the driver set the output current limit of
level before the next edge, producing pattern-dependent
OD
2. Intel Agilex I/O Features and Usage
(DC) level. Intel recommends that
V
I
VCCIO_PIO
. The pull-up resistor weakly holds the I/O to the
UG-20214 | 2019.04.02
level.
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